Video Lectures to support the textbook CMOS Circuit Design, Layout, and Simulation

1.1 The CMOS IC Design Process and 1.2 CMOS Background – ch1_1_2_video (29:43) and ch1_1_2_notes.pdf
1.3.part1 An Introduction to SPICE – ch1_1_3_p1_video (37:44) and ch1_1_3_p1.zip
1.3.part2 An Introduction to SPICE – ch1_1_3_p2_video (30:11) and ch1_1_3_p2.zip

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Chapter 2 – The Well

2.1 Patterning – 2.1.1 Patterning the N–well, 2.2 Laying Out the N–well – 2.2.1 Design Rules for the N–well, 2.3 Resistance Calculation – 2.3.1 The N–well Resistor – ch2_2_1_video (58:52) and ch2_2_1_notes.pdf
2.4 The N–well/Substrate Diode – 2.4.1 A Brief Introduction to PN Junction Physics, 2.4.2 Depletion Layer Capacitance, and 2.4.4 SPICE Modeling, and 2.5 The RC Delay through an N–well – ch2_2_4_video (63:58) and ch2_2_4_notes.pdf
2.4.3 Storage or Diffusion Capacitance and work examples from Ch. 2 – ch2_2_4_3_video (62:25) and ch2_2_4_3_notes.pdf

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Chapter 3 – The Metal Layers

3.1 The Bonding Pad – 3.1.1 Laying Out the Pad I, 3.2 Design and Layout Using the Metal Layers, 3.2.1 Metal 1 and Via1, 3.2.2 Parasitics Associated with the Metal Layers – ch3_3_1_video (59:45) and ch3_3_1_notes.pdf
3.2 Design and Layout Using the Metal Layers, 3.2.3 Current–Carrying Limitations, 3.2.4 Design Rules for the Metal Layers, 3.2.5 Contact Resistance, 3.3 Crosstalk and Ground Bounce, 3.2.1 Crosstalk, 3.2.2 Ground Bounce – ch3_3_2_video (70:17) and ch3_3_2_notes.pdf

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Chapter 4 – The Active and Poly Layers

4.1 Layout using the Active and Poly Layers – 4.1.1 Process Flow, 4.2 Connecting Wires to Poly and Active – ch4_4_1_video (64:05) and ch4_4_1_notes.pdf
4.2 Connecting Wires to Poly and Active – Layout of MOSFETs – ch4_4_2_video (72:02) and ch4_4_2_notes.pdf
4.3 Electrostatic Discharge (ESD) Protection – ch4_4_3_video (23:04) and ch4_4_3_notes.pdf

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Chapter 5 – Resistors, Capacitors, MOSFETs

5.1 Resistors and 5.2 Capacitors – ch5_5_1_video (26:48) and ch5_5_1_notes.pdf
5.2 Capacitors and more layout examples – ch5_5_2_video (60:48) and ch5_5_2_notes.pdf
5.3 MOSFETs and 5.4 Layout Examples – ch5_5_3_video (69:27) and ch5_5_3_notes.pdf

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Chapter 6 – MOSFET Operation

6.1 MOSFET Capacitance Overview/Review and MOSFET IV characteristics – ch6_6_1_video (63:35) and ch6_6_1_notes.pdf
6.2 The Threshold Voltage – ch6_6_2_video (69:38) and ch6_6_2_notes.pdf
6.3 IV Characteristics of MOSFETs – 6.3.1 MOSFET Operation in the Triode Region, 6.3.2 The Saturation Region – ch6_6_3_video (59:24) and ch6_6_3_notes.pdf
6.4 SPICE Modeling of the MOSFET – 6.4.1 Some SPICE Simulation Examples, 6.4.2 The Subthreshold Current, 6.5 Short–Channel MOSFETs, 6.5.1 MOSFET Scaling, 6.5.2 Short–Channel Effects, 6.5.3 SPICE Models for Our Short–Channel CMOS Process – ch6_6_4_video (69:38) and ch6_6_4_notes.pdf

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Chapter 7 – CMOS Fabrication

7.1.part1 CMOS Unit Processes – 7.1.1 Wafer Manufacture, 7.1.2 Thermal Oxidation, and 7.1.3 Doping Processes – ch7_7_1_p1_video (27:02) and ch7_7_1_p1_notes.pdf
7.1.part2 CMOS Unit Processes – 7.1.4 Photolithography, 7.1.5 Thin Film Removal, and 7.1.6 Thin Film Deposition – ch7_7_1_p2_video (31:03) and ch7_7_1_p2_notes.pdf
7.2.part1 CMOS Process Integration – 7.2.1 Frontend–of–the–Line Integration – ch7_7_2_p1_video (35:36) and ch7_7_2_p1_notes.pdf
7.2.part2 CMOS Process Integration – 7.2.2 Backend–of–the–Line Integration and 7.3 Backend Processes – ch7_7_2_p2_video (17:08) and ch7_7_2_p2_notes.pdf

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Chapter 8 – Electrical Noise: An Overview

8.1 Signals – 8.1.1 Power and Energy and 8.1.2 Power Spectral Density – ch8_8_1_video (39:00) and ch8_8_1_notes.pdf
8.2.part1 Circuit Noise – 8.2.1 Calculating and Modeling Circuit Noise – ch8_8_2_p1_video (32:17) and ch8_8_2_p1_notes.pdf
8.2.part2 Circuit Noise – 8.2.2 Thermal Noise – ch8_8_2_p2_video (37:43), ch8_8_2_p2_notes.pdf and ch8_8_2_p2.zip
8.2.part3 Circuit Noise – 8.2.3 Signal–to–Noise Ratio – ch8_8_2_p3_video (46:38) and ch8_8_2_p3_notes.pdf
8.2.part4 Circuit Noise – 8.2.4 Shot Noise – ch8_8_2_p4_video (33:38), ch8_8_2_p4_notes.pdf, and ch8_8_2_p4.zip
8.2.part5 Circuit Noise – 8.2.5 Flicker Noise – ch8_8_2_p5_video (31:09), ch8_8_2_p5_notes.pdf, and ch8_8_2_p5.zip
8.2.part6 Circuit Noise – 8.2.5 Flicker Noise and 8.2.6 Other Noise Sources – ch8_8_2_p6_video (24:52), ch8_8_2_p6_notes.pdf, and ch8_8_2_p6.zip
8.3.part1 Discussion – 8.3.1 Correlation – ch8_8_3_p1_video (24:29) and ch8_8_3_p1_notes.pdf
8.3.part2 Discussion – 8.3.2 Noise and Feedback and 8.3.3 Some Final Notes Concerning Notation – ch8_8_3_p2_video (27:04) and ch8_8_3_p2_notes.pdf

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Chapter 9 – Models for Analog Design

9.1.part1 Long–Channel MOSFETs – 9.1.1 The Square–Law Equations – ch9_9_1_p1_video (34:40), ch9_9_1_p1_notes.pdf, and ch9_9_1_p1.zip
9.1.part2 Long–Channel MOSFETs – 9.1.2 Small–Signal Models – ch9_9_1_p2_video (41:15), ch9_9_1_p2_notes.pdf, and ch9_9_1_p2.zip
9.1.part3 Long–Channel MOSFETs – Example 9.5 – ch9_9_1_p3_video (43:30), ch9_9_1_p3_notes.pdf, and ch9_9_1_p3.zip
9.1.part4 Long–Channel MOSFETs – gmb, fT, and ro – ch9_9_1_p4_video (40:13), ch9_9_1_p4_notes.pdf, and ch9_9_1_p4.zip
9.1.part5 Long–Channel MOSFETs – 9.1.3 Temperature Effects – ch9_9_1_p5_video (36:35), ch9_9_1_p5_notes.pdf, and ch9_9_1_p5.zip
9.2 Short–Channel MOSFETs – 9.2.1 General Design (A Starting Point) and 9.2.2 Specific Design (A Discussion) – ch9_9_2_p1_video (33:57), ch9_9_2_p1_notes.pdf, and ch9_9_2_p1.zip
9.3 MOSFET Noise Modeling – ch9_9_3_video (16:06), ch9_9_3_notes.pdf, and ch9_9_3.zip

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Chapter 10 – Models for Digital Design

10.1.part1 The Digital MOSFET Model – Miller Capacitance, and 10.1.1 Capacitive Effects – ch10_10_1_p1_video (55:59), ch10_10_1_p1_notes.pdf, and ch10_10_1_p1.zip
10.1.part2 The Digital MOSFET Model – 10.1.2 Process Characteristic Time Constant, and 10.1.3 Delay and Transition Times and 10.1.4 General Digital Design – ch10_10_1_p2_video (29:54), ch10_10_1_p2_notes.pdf, and ch10_10_1_p2.zip
10.2 The MOSFET Pass Gate – 10.2.1 Delay through a Pass Gate, 10.2.2 Delay through Series–Connected PGs, and 10.3 A Final Comment Concerning Measurements – ch10_10_2_video (37:31), ch10_10_2_notes.pdf, and ch10_10_2.zip

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Chapters 11–15: Digital Design

Chapter 11 – The Inverter

11.1 DC Characteristics – ch11_11_1_video (58:09) and ch11_11_1_notes.pdf
11.2 Switching Characteristics – ch11_11_2_video (62:28) and ch11_11_2_notes.pdf
11.4 (Inverter) Sizing for Large Capacitive Loads – ch11_11_4_video (71:22) and ch11_11_4_notes.pdf

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Chapter 12 – Static Logic Gates

12.1 (Static Logic Gates) DC Characteristics of the NAND and NOR Gates, 12.2 Layout of the NAND and NOR Gates, and 12.3 Switching Characteristics – ch12_12_1_video (67:56) and ch12_12_1_notes.pdf
12.4 Complex CMOS Logic Gates – ch12_12_4_video (46:42) and ch12_12_4_notes.pdf

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Chapter 13 – Clocked Circuits

13.1 The CMOS TG, 13.2 Applications of the Transmission Gate, 13.3 Latches and Flip–Flops – ch13_13_1_video (63:35) and ch13_13_1_notes.pdf

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Chapter 14 – Dynamic Logic Gates

14.1 Fundamentals of Dynamic Logic – 14.1.1 Charge Leakage, 14.1.2 Simulating Dynamic Circuits, 14.1.3 Nonoverlapping Clock Generation, and 14.1.4 CMOS TG in Dynamic Circuits – ch14_14_1_video (40:45) and ch14_14_1_notes.pdf

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Chapter 15 – VLSI Layout Examples

15.1 Chip Layout – ch15_15_1_video (22:23) and ch15_15_1_notes.pdf

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Chapters 16–19: Advanced Digital Design

Chapter 16 – Memory Circuits

16.1.part1 Array Architectures and 16.1.1 Sensing Basics – ch16_16_1_p1_video (60:11) and ch16_16_1_p1_notes.pdf
16.1.part2 Array Architectures, 16.1.2 The Folded–Array, and 16.1.3 Chip Organization – ch16_16_1_p2_video (53:03) and ch16_16_1_p2_notes.pdf
16.2 Peripheral Circuits, 16.2.1 Sense Amplifier Design, and 16.2.2 Row/Column Decoders – ch16_16_2_video (67:57) and ch16_16_2_notes.pdf
16.3.part1 Memory Cells, 16.3.1 The SRAM Cell, and 16.3.2 Read–Only Memory (ROM) – ch16_16_3_p1_video (59:23) and ch16_16_3_p1_notes.pdf
16.3.part2 Memory Cells and 16.3.3 Floating Gate Memory – ch16_16_3_p2_video (62:08) and ch16_16_3_p2_notes.pdf

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Chapter 17 – Sensing using DS Modulation

17.1 Qualitative Discussion, 17.1.1 Examples of DSM, and 17.1.2 Using DSM for Sensing in Flash Memory – ch17_17_1_video (57:10) and ch17_17_1_notes.pdf
17.2 Sensing Resistive Memory – ch17_17_2_video (62:55) and ch17_17_2_notes.pdf
17.3 Sensing in CMOS Imagers – ch17_17_3_video (62:57) and ch17_17_3_notes.pdf

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Chapter 18 – Special Purpose CMOS Circuits

18.1 The Schmitt Trigger, 18.1.1 Design of the Schmitt Trigger, 18.1.2 Applications of the Schmitt Trigger – ch18_18_1_video (60:08) and ch18_18_1_notes.pdf
18.2 Multivibrator Circuits, 18.2.1 The Monostable Multivibrator, 18.2.2 The Astable Multivibrator, 18.3 Input Buffers, 18.3.1 Basic Circuits, 18.3.2 Differential Circuits, 18.3.3 DC Reference, and 18.3.4 Reducing Buffer Input Resistance – ch18_18_2_video (73:45) and ch18_18_2_notes.pdf
18.4 Charge Pumps (Voltage Generators), 18.4.1 Increasing the Output Voltage, and 18.4.2 Generating Higher Voltages: The Dickson Charge Pump – ch18_18_4_video (63:06) and ch18_18_4_notes.pdf

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Chapter 19 – Digital Phase–Locked Loops

19.1 The Phase Detector, 19.1.1 The XOR Phase Detector, and 19.1.2 The Phase Frequency Detector – ch19_19_1_p1_video (64:47) and ch19_19_1_p1_notes.pdf
19.2 The Voltage–Controlled Oscillator, 19.2.1 The Current–Starved VCO, 19.2.2 Source–Coupled VCOs, 19.3 The Loop Filter, and 19.3.1 XOR DPLL – ch19_19_2_video (63:52) and ch19_19_2_notes.pdf
19.3 The Loop Filter, 19.3.1 XOR DPLL, and 19.3.2 PFD DPLL – ch19_19_3_video (66:16) and ch19_19_3_notes.pdf
19.4 System Considerations and 19.4.1 Clock Recovery from NRZ Data – ch19_19_4_video (47:45) and ch19_19_4_notes.pdf
19.5 Delay–Locked Loops – ch19_19_5_video (49:27) and ch19_19_5_notes.pdf
19.6 Some Examples, 19.6.1 A 2 GHz DLL, and 19.6.2 A 1 Gbit/s Clock–Recovery Circuit – ch19_19_6_video (42:29) and ch19_19_6_notes.pdf

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Chapters 20–24: Analog Design

Chapter 20 – Current Mirrors

20.1.part1 Current Mirrors – 20.1.1 Long–Channel Design and 20.1.2 Matching Currents in the Mirror – ch20_20_1_p1_video (45:28), ch20_20_1_p1_notes.pdf, and ch20_20_1_p1.zip
20.1.part2 Current Mirrors – 20.1.2 Matching Currents in the Mirror and 20.1.3 Biasing the Current Mirror – ch20_20_1_p2_video (50:01), ch20_20_1_p2_notes.pdf, and ch20_20_1_p2.zip
20.1.part3 Current Mirrors – 20.1.3 Biasing the Current Mirror (the Beta–Multiplier Reference, BMR) and 20.1.4 Short–Channel Design – ch20_20_1_p3_video (42:31), ch20_20_1_p3_notes.pdf, and ch20_20_1_p3.zip
20.1.part4 Current Mirrors – 20.1.5 Temperature Behavior and 20.1.6 Biasing in the Subthreshold Region – ch20_20_1_p4_video (38:35), ch20_20_1_p4_notes.pdf, and ch20_20_1_p4.zip
20.2.part1 Cascoding the Current Mirror – 20.2.1 The Simple Cascode and 20.2.2 Low–Voltage (Wide–Swing) Cascode – ch20_20_2_p1_video (36:05), ch20_20_2_p1_notes.pdf, and ch20_20_2_p1.zip
20.2.part2 Cascoding the Current Mirror – 20.2.3 Wide–Swing, Short–Channel Design and 20.2.4 Regulated Drain Current Mirror – ch20_20_2_p2_video (29:00), ch20_20_2_p2_notes.pdf, and ch20_20_2_p2.zip
20.3 Biasing Circuits – 20.3.1 Long–Channel Biasing Circuits, 20.3.2 Short–Channel Biasing Circuits, and 20.3.3 A Final Comment – ch20_20_3_video (31:31), ch20_20_3_notes.pdf, and ch20_20_3.zip
Noise in Current Mirrors – ch20_noise_video (26:37), ch20_noise_notes.pdf, and ch20_noise.zip

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Chapter 21 – Amplifiers

21.1 Gate–Drain–Connected Loads – ch21_21_1_video (58:25) and ch21_21_1_notes.pdf
21.2.part1 Current Source Loads – 21.2.1 Common–Source Amplifier – ch21_21_2_p1_video (1:07:33), ch21_21_2_p1_notes.pdf, and ch21_21_2_p1.zip
21.2.part2 Current Source Loads – 21.2.2 The Cascode Amplifier, 21.2.3 The Common–Gate Amplifier, and 21.2.4 The Source Follower (Common–Drain Amplifier) – ch21_21_2_p2_video (55:38), ch21_21_2_p2_notes.pdf, and ch21_21_2_p2.zip
21.3 The Push–Pull Amplifier – ch21_21_3_video (58:39), ch21_21_3_notes.pdf, and ch21_21_3.zip
Noise in Amplifiers – ch21_noise_video (35:30), ch21_noise_notes.pdf, and ch21_noise.zip

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Chapter 22 – Differential Amplifiers

22.1.part1 The Source–Coupled Pair, 22.1.1 DC Operation, and 22.1.2 AC Operation – ch22_22_1_p1_video (73:03), ch22_22_1_p1_notes.pdf, and ch22_22_1_p1.zip
22.1.part2 The Source–Coupled Pair, 22.1.3 Common–Mode Rejection Ratio, 22.1.4 Matching Considerations, 22.1.6 Slew–Rate Limitations, and 22.3 Cascode Loads (The Telescopic Diff–Amp) – ch22_22_1_p2_video (69:31), ch22_22_1_p2_notes.pdf, and ch22_22_1_p2.zip
Noise in Differential Amplifiers – ch22_noise_video (16:28), ch22_noise_notes.pdf, and ch22_noise.zip

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Chapter 23 – Voltage References

23.1 Voltage References, 23.1.1 The Resistor–MOSFET Divider, 23.1.2 The MOSFET–Only Voltage Divider, and 23.1.3 Self–Biased Voltage References – ch23_23_1_video (51:44), ch23_23_1_notes.pdf, and ch23_23_1.zip
23.2.part1 Parasitic Diode–Based References and 23.2.1 Long–Channel BGR Design – ch23_23_2_p1_video (71:29), ch23_23_2_p1_notes.pdf, and ch23_23_2_p1.zip
23.2.part2 Parasitic Diode–Based References and 23.2.2 Short–Channel BGR Design – ch23_23_2_p2_video (18:26), ch23_23_2_p2_notes.pdf, and ch23_23_2_p2.zip

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Chapter 24 – Operational Amplifiers I

24.1.part1 The Two–Stage Op–Amp – ch24_24_1_p1_video (31:22), ch24_24_1_p1_notes.pdf, and ch24_24_1_p1.zip
24.1.part2 The Two–Stage Op–Amp – ch24_24_1_p2_video (67:03), ch24_24_1_p2_notes.pdf, and ch24_24_1_p2.zip
24.1.part3 The Two–Stage Op–Amp – ch24_24_1_p3_video (40:09), ch24_24_1_p3_notes.pdf, and ch24_24_1_p3.zip
24.2 An Op–Amp with Output Buffer – ch24_24_2_video (14:32), ch24_24_2_notes.pdf, and ch24_24_2.zip
24.3 The Operational Transconductance Amplifier (OTA) – ch24_24_3_video (57:08), ch24_24_3_notes.pdf, and ch24_24_3.zip
24.4 Gain–Enhancement – ch24_24_4_video (30:29), ch24_24_4_notes.pdf, and ch24_24_4.zip
24.5.part1 Some Examples and Discussions - ch24_24_5_p1_video (51:51) and ch24_24_5_p1_notes.pdf
24.5.part2 Some Examples and Discussions - ch24_24_5_p2_video (37:59), ch24_24_5_p2_notes.pdf, and ch24_24_5_p2.zip

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Chapters 25-31: Advanced Analog Design

Chapter 25 – Dynamic Analog Circuits

25.1 The MOSFET Switch, 25.1.1 Sample-and-Hold Circuits, 25.2 Fully-Differential Circuits, and 25.2.1 A Fully-Differential Sample-and-Hold - ch25_25_1_video (54:25) and ch25_25_1_notes.pdf
25.3 Switched-Capacitor Circuits and 25.3.1 Switched-Capacitor Integrator - ch25_25_3_video (32:37) and ch25_25_3_notes.pdf
25.4 Circuits - ch25_25_4_video (39:06) and ch25_25_4_notes.pdf

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Chapter 26 – Operational Amplifiers II

26.1 Biasing for Power and Speed, 26.1.1 Device Characteristics, and 26.1.2 Biasing Circuit - ch26_26_1_video (11:54), ch26_26_1_notes.pdf, and ch26_26_1.zip
26.2 Basic Concepts - ch26_26_2_video (38:20), ch26_26_2_notes.pdf, and ch26_26_2.zip
26.3 Basic Op-Amp Design - ch26_26_3_video (64:54), ch26_26_3_notes.pdf, and ch26_26_3.zip
26.4 Op-Amp Design Using Switched-Capacitor CMFB - ch26_26_4_video (30:07), ch26_26_4_notes.pdf, and ch26_26_4.zip

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Chapter 27 – Nonlinear Analog Circuits

27.1 Basic CMOS Comparator Design, 27.1.1 Characterizing the Comparator, and 27.1.2 Clocked Comparators - ch27_27_1_video (63:08) and ch27_27_1_notes.pdf
27.2 Adaptive Biasing, 27.3 Analog Multipliers, 27.3.1 The Multiplying Quad, and 27.3.2 Multiplier Design Using Squaring Circuits - ch27_27_2_video (33:43) and ch27_27_2_notes.pdf

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Chapter 28 – Data Converter Fundamentals

28.1 Analog Versus Discrete Time Signals, 28.2 Converting Analog Signals to Digital Signals, 28.3 Sample-and-Hold (S/H) Characteristics, 28.4 Digital-to-Analog (DAC) Specifications, and 28.5 Analog-to-Digital Converter (ADC) Specifications - ch28_28_1_video (74:48) and ch28_28_1_notes.pdf

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Chapter 29 – Data Converter Architectures

29.1.part1 DAC Architectures, 29.1.1 Digital Input Code, 29.1.2 Resistor String, 29.1.3 R-2R Ladder Networks, and 29.1.4 Current Steering - ch29_29_1_p1_video (60:29) and ch29_29_1_p1_notes.pdf
29.1.part2 DAC Architectures, 29.1.5 Charge-Scaling DACs, 29.1.6 Cyclic DAC, and 29.1.7 Pipeline DAC - ch29_29_1_p2_video (66:53) and ch29_29_1_p2_notes.pdf
29.2.part1 ADC Architectures, 29.2.1 Flash, 29.2.2 The Two-Step Flash ADC, and 29.2.3 The Pipeline ADC - ch29_29_2_p1_video (58:55) and ch29_29_2_p1_notes.pdf
29.2.part2 ADC Architectures, 29.2.4 Integrating ADCs, 29.2.5 The Successive Approximation ADC, and 29.2.6 The Oversampling ADC - ch29_29_2_p2_video (67:48) and ch29_29_2_p2_notes.pdf

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Chapter 30 – Implementing Data Converters

30.1 Implementing Data Converters, 30.1 R-2R Topologies for DACs, 30.1.1 The Current-Mode R-2R DAC, 30.1.2 The Voltage-Mode R-2R DAC, 30.1.3 A Wide-Swing Current-Mode R-2R DAC, and 30.1.4 Topologies Without an Op-Amp - ch30_30_1_video (62:29) and ch30_30_1_notes.pdf
30.2.part1 Op-Amps in Data Converters, 30.2.1 Op-Amp Gain, and 30.2.2 Op-Amp Unity Gain Frequency – ch30_30_2_p1_video (51:40), ch30_30_2_p1_notes.pdf, and ch30_30_2_p1.zip
30.3 Implementing ADCs, 30.3.1 Implementing the S/H, 30.3.2 The Cyclic ADC, and 30.3.3 The Pipeline ADC - ch30_30_3_video (60:56) and ch30_30_3_notes.pdf

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Chapter 31 – Feedback Amplifiers

31.1 The Feedback Equation - ch31_31_1_video (41:14) and ch31_31_1_notes.pdf
31.2 Properties of Negative Feedback on Amplifier Design, 31.2.1 Gain Desensitivity, 31.2.2 Bandwidth Extension, 31.2.3 Reduction in Nonlinear Distortion, and 31.2.4 Input and Output Impedance Control - ch31_31_2_video (58:12) and ch31_31_2_notes.pdf
31.3.part1 Recognizing Feedback Topologies, 31.3.1 Input Mixing, 31.3.2 Output Sampling, 31.3.3 The Feedback Network - ch31_31_3_p1_video (43:05) and ch31_31_3_p1_notes.pdf
31.3.part2 Recognizing Feedback Topologies, 31.3.4 Calculating Open-Loop Parameters, and 31.3.5 Calculating Closed-Loop Parameters - ch31_31_3_p2_video (29:13) and ch31_31_3_p2_notes.pdf
31.4 The Voltage Amp (Series-Shunt Feedback) - ch31_31_4_video (1:01:29), ch31_31_4_notes.pdf, and ch31_31_4.zip
31.5 The Transimpedance Amp (Shunt-Shunt Feedback) - ch31_31_5_video (58:12), ch31_31_5_notes.pdf, and ch31_31_5.zip
31.5.1 Simple Feedback Using a Gate-Drain Resistor - ch31_31_5_1_video (46:54), ch31_31_5_1_notes.pdf, and ch31_31_5_1.zip
31.6 The Transconductance Amp (Series-Series Feedback) - ch31_31_6_video (43:35),ch31_31_6_notes.pdf, and ch31_31_6.zip
31.7 The Current Amplifier (Shunt-Series Feedback) - ch31_31_7_video (59:55), ch31_31_7_notes.pdf, and ch31_31_7.zip
31.8 Stability and 31.8.1 The Return Ratio - ch31_31_8_video (40:16), ch31_31_8_notes.pdf, and ch31_31_8.zip
31.9 Design Examples, 31.9.1 Voltage Amplifiers, and 31.9.2 A Transimpedance Amplifier - ch31_31_9_video (44:02),ch31_31_9_notes.pdf, and ch31_31_9.zip

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