CMOS: Circuit Design, Layout, and Simulation

General book information

Published by Wiley-IEEE. Browse the book’s table of contents or index.

ISBN 978-0-470-22941-5, Revised 2nd Edition, 2008

The book’s author is R. Jacob Baker. Buy at Amazon.com

Errata and (some) email correspondence are found here.

Instructors may request an evaluation copy here.
 

Layout software and MOSIS information

Cadence Design System – Ubiquitous commercial CAD system with a generous university program

Electric VLSI Design System – free and powerful CAD system for chip design (schematics, layout, DRC, LVS, ERC, etc.)

The Windows LAyout System for Individuals (LASI) is located here.

Information on submitting chips to MOSIS can be found here.

 

SPICE software and MOSFET models

The book’s SPICE simulation examples are available in LTspice (*.asc), WinSpice (*.cir), or HSPICE (*.sp) formats.

The 50 nm and 1 um MOSFET models are found in cmosedu_models.txt (see also, BSIM4 manual).

  

Check out the videos here!

SPICE

Cadence

Electric

Figures (PDF)

Figures (ppt)

Solutions

Problems*

Chaps 1-10: CMOS Fundamentals

 

readme.pdf

using LTspice

Acrobat

Power point

To book probs

Symbols.doc

Chapter 1 – Introduction to CMOS Design

Ch1_spice.zip

Ch1_cadence.zip

Ch1_electric.zip

Ch1_figs.pdf

Ch1_figs.ppt

Solns_1.pdf

Ch1_hw.doc

Chapter 2 – The Well

Ch2_spice.zip

Ch2_cadence.zip

Ch2_electric.zip

Ch2_figs.pdf

Ch2_figs.ppt

Solns_2.pdf

Ch2_hw.doc

Chapter 3 – The Metal Layers

Ch3_spice.zip

Ch3_cadence.zip

Ch3_electric.zip

Ch3_figs.pdf

Ch3_figs.ppt

Solns_3.pdf

Ch3_hw.doc

Chapter 4 – The Active and Poly Layers

Ch4_spice.zip

Ch4_cadence.zip

Ch4_electric.zip

Ch4_figs.pdf

Ch4_figs.ppt

Solns_4.pdf

Ch4_hw.doc

Chapter 5 – Resistors, Capacitors, MOSFETs

Ch5_spice.zip

Ch5_cadence.zip

Ch5_electric.zip

Ch5_figs.pdf

Ch5_figs.ppt

Solns_5.pdf

Ch5_hw.doc

Chapter 6 – MOSFET Operation

Ch6_spice.zip

Ch6_cadence.zip

Ch6_electric.zip

Ch6_figs.pdf

Ch6_figs.ppt

Solns_6.pdf

Ch6_hw.doc

Chapter 7 – CMOS Fabrication

Ch7_spice.zip

Ch7_cadence.zip

Ch7_electric.zip

Ch7_figs.pdf

Ch7_figs.ppt

Solns_7.pdf

Ch7_hw.doc

Chapter 8 – Electrical Noise: An Overview

Ch8_spice.zip

Ch8_cadence.zip

Ch8_electric.zip

Ch8_figs.pdf

Ch8_figs.ppt

Solns_8.pdf

Ch8_hw.doc

Chapter 9 – Models for Analog Design

Ch9_spice.zip

Ch9_cadence.zip

Ch9_electric.zip

Ch9_figs.pdf

Ch9_figs.ppt

Solns_9.pdf

Ch9_hw.doc

Chapter 10 – Models for Digital Design

Ch10_spice.zip

Ch10_cadence.zip

Ch10_electric.zip

Ch10_figs.pdf

Ch10_figs.ppt

Solns_10.pdf

Ch10_hw.doc

Chaps 11-15 Digital Design

 

 

 

 

 

 

 

Chapter 11 – The Inverter

Ch11_spice.zip

Ch11_cadence.zip

Ch11_electric.zip

Ch11_figs.pdf

Ch11_figs.ppt

Solns_11.pdf

Ch11_hw.doc

Chapter 12 – Static Logic Gates

Ch12_spice.zip

Ch12_cadence.zip

Ch12_electric.zip

Ch12_figs.pdf

Ch12_figs.ppt

Solns_12.pdf

Ch12_hw.doc

Chapter 13 – Clocked Circuits

Ch13_spice.zip

Ch13_cadence.zip

Ch13_electric.zip

Ch13_figs.pdf

Ch13_figs.ppt

Solns_13.pdf

Ch13_hw.doc

Chapter 14 – Dynamic Logic Gates

Ch14_spice.zip

Ch14_cadence.zip

Ch14_electric.zip

Ch14_figs.pdf

Ch14_figs.ppt

Solns_14.pdf

Ch14_hw.doc

Chapter 15 – VLSI Layout Examples

Ch15_spice.zip

Ch15_cadence.zip

Ch15_electric.zip

Ch15_figs.pdf

Ch15_figs.ppt

Solns_15.pdf

Ch15_hw.doc

Chaps 16-19 Advanced Digital Design

 

 

 

 

 

 

 

Chapter 16 – Memory Circuits

Ch16_spice.zip

Ch16_cadence.zip

Ch16_electric.zip

Ch16_figs.pdf

Ch16_figs.ppt

Solns_16.pdf

Ch16_hw.doc

Chapter 17 – Sensing using DS Modulation

Ch17_spice.zip

Ch17_cadence.zip

Ch17_electric.zip

Ch17_figs.pdf

Ch17_figs.ppt

Solns_17.pdf

Ch17_hw.doc

Chapter 18 – Special Purpose CMOS Circuits

Ch18_spice.zip

Ch18_cadence.zip

Ch18_electric.zip

Ch18_figs.pdf

Ch18_figs.ppt

Solns_18.pdf

Ch18_hw.doc

Chapter 19 – Digital Phase-Locked Loops

Ch19_spice.zip

Ch19_cadence.zip

Ch19_electric.zip

Ch19_figs.pdf

Ch19_figs.ppt

Solns_19.pdf

Ch19_hw.doc

Chaps 20-24: Analog Design

 

 

 

 

 

 

 

Chapter 20 – Current Mirrors

Ch20_spice.zip

Ch20_cadence.zip

Ch20_electric.zip

Ch20_figs.pdf

Ch20_figs.ppt

Solns_20.pdf

Ch20_hw.doc

Chapter 21 – Amplifiers

Ch21_spice.zip

Ch21_cadence.zip

Ch21_electric.zip

Ch21_figs.pdf

Ch21_figs.ppt

Solns_21.pdf

Ch21_hw.doc

Chapter 22 – Differential Amplifiers

Ch22_spice.zip

Ch22_cadence.zip

Ch22_electric.zip

Ch22_figs.pdf

Ch22_figs.ppt

Solns_22.pdf

Ch22_hw.doc

Chapter 23 – Voltage References

Ch23_spice.zip

Ch23_cadence.zip

Ch23_electric.zip

Ch23_figs.pdf

Ch23_figs.ppt

Solns_23.pdf

Ch23_hw.doc

Chapter 24 – Operational Amplifiers I

Ch24_spice.zip

Ch24_cadence.zip

Ch24_electric.zip

Ch24_figs.pdf

Ch24_figs.ppt

Solns_24.pdf

Ch24_hw.doc

Chaps 25-29: Advanced Analog Design

 

 

 

 

 

 

 

Chapter 25 – Dynamic Analog Circuits

Ch25_spice.zip

Ch25_cadence.zip

Ch25_electric.zip

Ch25_figs.pdf

Ch25_figs.ppt

Solns_25.pdf

Ch25_hw.doc

Chapter 26 – Operational Amplifiers II

Ch26_spice.zip

Ch26_cadence.zip

Ch26_electric.zip

Ch26_figs.pdf

Ch26_figs.ppt

Solns_26.pdf

Ch26_hw.doc

Chapter 27 – Nonlinear Analog Circuits

Ch27_spice.zip

Ch27_cadence.zip

Ch27_electric.zip

Ch27_figs.pdf

Ch27_figs.ppt

Solns_27.pdf

Ch27_hw.doc

Chapter 28 – Data Converter Fundamentals

Ch28_spice.zip

Ch28_cadence.zip

Ch28_electric.zip

Ch28_figs.pdf

Ch28_figs.ppt

Solns_28.pdf

Ch28_hw.doc

Chapter 29 – Data Converter Architectures

Ch29_spice.zip

Ch29_cadence.zip

Ch29_electric.zip

Ch29_figs.pdf

Ch29_figs.ppt

Solns_29.pdf

Ch29_hw.doc

 

*These problems are made available, in addition to the textbook problems, but without written solutions since they would end up posted on the web.

 

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