Circuit Design, Layout, and Simulation, Third Edition
Published by Wiley-IEEE Press, ISBN 9780470881323, 3rd Edition, 2010.
The book’s author is R. Jacob Baker.
Errata and (some) email correspondence are found here.
Instructors may request an evaluation copy here.
and Simulation Examples
Design System – ubiquitous commercial tools.
VLSI Design System – free and powerful CAD system for chip design (schematics,
layout, DRC, LVS, ERC, etc.).
– the LAyout System for Individuals.
Mentor Graphics – IC design, verification, design-for-manufacturability, and test technologies.
Analog/Mixed-Signal/RF EDA – easy-to-use tools with good process design kit
MOSFET Models, and MOSIS Information
The book’s SPICE simulation examples are available
at HSPICE, LTspice, PSpice, and WinSpice.
The 50 nm and 1 um MOSFET models are found in cmosedu_models.txt (see
also, BSIM4 manual).
Information on generating a GDSII (stream) file and help on submitting chips
to MOSIS can be found here.
Tutorials, and Videos
Download supporting material in:
SPICE.zip, Solutions.zip, Silvaco.zip, Mentor.zip, Cadence_IC61.zip, Cadence_IC51.zip, Figures.zip, and Electric.zip.
Tutorials from CMOSedu.com: Bad design, Cadence, Electric VLSI, LTspice, and Silvaco EDA.
Videos are located here, MATLAB examples are here, and Verilog-AMS
examples are found here.
edition’s supporting material is found at the bottom of the webpage here.
Return to the CMOSedu.com page