Circuit Design, Layout, and Simulation, Third Edition

General Book Information 

Published by Wiley-IEEE Press, ISBN 9780470881323, 3rd Edition, 2010.

The book’s author is R. Jacob Baker.

Errata and (some) email correspondence are found here.



Instructors may request an evaluation copy here.


Design, Layout, and Simulation Examples

Cadence Design System – ubiquitous commercial tools.

Electric VLSI Design System – free and powerful CAD system for chip design (schematics, layout, DRC, LVS, ERC, etc.).

LASI – the LAyout System for Individuals.

Mentor Graphics – IC design, verification, design-for-manufacturability, and test technologies.

Silvaco Analog/Mixed-Signal/RF EDA – easy-to-use tools with good process design kit (PDK) availability.


SPICE Software, MOSFET Models, and MOSIS Information

The book’s SPICE simulation examples are available at HSPICE, LTspice, PSpice, and WinSpice.

The 50 nm and 1 um MOSFET models are found in cmosedu_models.txt (see also, BSIM4 manual).

Information on generating a GDSII (stream) file and help on submitting chips to MOSIS can be found here.


Downloads, Tutorials, and Videos

Download supporting material in:,,,,,,, and

Tutorials from Bad design, Cadence, Electric VLSI, LTspice, and Silvaco EDA.

    Videos are located hereMATLAB examples are here, and Verilog-AMS examples are found here.

      The first edition’s supporting material is found at the bottom of the webpage here.


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