Current
(and Past) Research Interests
Currently my research focuses on:
- Design flow and techniques for fabricating safe and
secure (trusted) integrated circuits
- Investigating 3D packaging and capacitive interconnects
to reduce power consumption in semiconductor memories
- Chip-scale methods to implement chemical and
biological sensors using CMOS
- Design of readout integrated circuits (ROICs) for use
with focal plane arrays (FPAs)
- Heterogeneous integration of III-V photonic devices
(e.g. FPAs and VCSELs) with CMOS
- Analog and mixed-signal circuit design for
communication systems, synchronization, and data conversion especially
using the K-Delta-1-Sigma
modulator
- The design of writing and sensing circuitry for emerging
nonvolatile memory technologies, focal planes, and displays (arrays) in
nascent nanotechnologies (e.g. magnetic, chalcogenide)
- Reconfigurable electronics design using nascent
memory technologies
- Finding an electronic, that is, no mechanical component,
replacement for the hard disk drive using nascent fabrication technologies
- Methods to deliver circuit design education to
industry and off-campus students, see videos here
For specific details of the work see the resulting patents, talks/papers, and dissertations/theses.
Some recent funding is listed below. In-kind, equipment,
and other non-contract/grant funding [e.g., MOSIS support, money for travel for
invited talks, etc.] is not listed.
- Campbell, K.
A. and Baker, R. J., (2009-2012) "Reconfigurable Electronics and
Non-Volatile Memory Research" Air Force Research Laboratory,
$2,790,081
- Baker, R. J.,
(2011-2012) “Monolithic CMOS LADAR Focal Plane Array (FPA) with
a Photonic High-Speed Output Interface,” U.S. Air Force/DOD, $50,002
- Baker, R. J.,
(2011) “Readout-Integrated Circuit (ROIC) Development in Support of
Corrugated Quantum Well Infrared Photo-detector (C-QWIP) Focal Plane
Arrays (FPA) for Tactical Applications,” U.S. Army, $27,000
- Baker, R. J.,
(2010-2011) “Dual Well Focal Plane Array (FPA) Sensor,” U.S. Navy, $31,500
- Campbell, K.
A., Baker, R. J., Peloquin, J., and Teasdale, J. (2008-2010) “Radiation
Resistant Phase Change Memory and Reconfigurable Electronics,” NASA.
$1,500,000
- Campbell, K.
A., Baker, R. J., Peloquin, J., and Teasdale, J. (2007) “Reliability
Investigations of Radiation Resistant, Multi-State Phase-Change Memory,”
NASA. $726,768
- Baker, R. J. et. al., (2006-2010) “Establishment of a Doctoral
Degree Program in Electrical and Computer Engineering in Electrical and
Computer Engineering,” Micron Foundation. $5,000,000
- Baker, R. J.
(2005-2006) "Advanced Processing Techniques for Fabrication of 3D
Microstructures for Future Electronic Devices," DARPA,
N66001-01-C-8034, $125,000
- Baker, R. J.
(2004-2005) "Multi-Purpose Sensors for Detection and Analysis of Contaminants"
EPA, X-97031102, $75,000
- Baker, R. J.
(2001-2006) Multi-University Research Initiative (MURI), “The effects of
radio frequency pulses on electronic circuits and systems,” Air Force
Research Laboratory, $350,000
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Example research and development work is seen below.
Again, for specific details of the work see the resulting patents, talks/papers, and dissertations/theses
in addition to the links seen below.
- Laid
out a test chip using TowerJazz’s CA18QD process
to characterize APDs
and LNAs for LADAR applications, (USAF,
2012)
- Designed
CMOS silicon
avalanche photodetectors (APDs) and laid out a test chip, in On’s C5 process, to characterize the APDs for use in
high-speed imaging and LADAR applications, (FLIR, 2011-2012)
- Worked
on the design of readout
integrated circuits (ROICs) for use with various focal plane arrays (FPAs),
(Aerius Photonics,
2010-2011)
- Design
using the Memristor to implement reconfigurable analog electronics with
CMOS technology, (AFRL,
2011)
- Designed
a Flash LIDAR ROIC unit cell, (Areté Associates, 2010)
- Worked
with Sun’s/Oracle’s VLSI Research Group on the design of memory
chips/systems for applications using proximity communication, wide IOs,
and 3D packaging, (Oracle, Inc.,
2009-2010)
- NMOS
voltage and current references, charge pumps, voltage regulators, and
power up/down circuits for phase-change memory chips, (Contour Semiconductor, Inc.,
2009-2010)
- Using
the K-Delta-1-Sigma modulator
for Gsample/s data converter design
- Sensing schemes for new memory technologies
- Circuit
design and 3D packaging applications of Thru-Silicon Vias,
(DARPA, 2000-2011)
- Low-overhead
voltage regulators for DRAM memory chips
- High-speed
digital timing circuits including input buffers, delay-locked loops and
comparators
- Design
of CMOS imager pixel and periphery circuitry
- Design
of delta-sigma
imager sensors
- Pipelined
ADCs for CMOS imaging chips
- Noise-shaping
analog-to-digital conversion
- Layout
techniques to improve circuit performance
- Designed
and tested delta-sigma
sensing circuits for drastically improving sensing in Flash memory (35
nm), (Micron Technology, Inc.,
2008)
- Designed
Schottky diodes in a standard CMOS process for
use in radio-frequency applications
- A
high-speed low-power 10-bit DAC
(design done at the request of a VC firm, 1999)
- 64 MHz
DAC for power
line communications (ITRAN
Communications, 1999)
- High-speed
clocked comparator
for spread spectrum communications (ITRAN
Communications, 1999)
- Pre-amplifier
with clipped output (ITRAN
Communications, 1999)
- Power op-amp for
driving 30 ohm equivalent load (ITRAN
Communications, 1999)
- An R-2R type 10-bit
(and an 8-bit version) DAC in 0.18 um CMOS (Amkor Wafer Fabrication Services, 1999)
- A PLL
for an embedded
DRAM chip (Micron Technology Inc., 1999)
- Designs
ranging from pipeline ADCs to attempts at implementing switching power
supplies in memory chips, (Micron
Technology, Inc., 1998-2008)
- Low-power
CMOS Crystal
Oscillator (Tower RDT ASIC center, Israel, 1998)
- High
sensitivity comparator
with 0.5 mV hysteresis (Tower RDT ASIC center, Israel, 1998)
- Pixel clock generator
from a PCI clock (Rendition,
Santa Clara, 1998).
- CMOS PLL design in
submicron CMOS (Amkor Wafer
Fabrication Services, 1998)
- Design
of double-data rate (DDR) circuits to transition SDRAM to DDR-SDRAM (Micron
Technology, Inc., 1998-2000)
- High-speed
(>500 Mbits/s), low-skew fully-differential
digital receiver/transmitter design (Micron
Technology, Inc., 1998)
- Test DLL for data
rates up to 500 Mbits/s (Micron Technology,
1998)
- CMOS pecision voltage reference without substrate injection
(Micron Technology, 1997)
- Power up/down
circuit for a modem
using a bandgap and an MOS voltage reference (Tower Semiconductor,
Israel, 1997)
- 10 MHz
8-bit D/A converter
that can drive low resistance load (Tower Semiconductor, Israel, 1997)
- High-speed
modem receiver
(Tower Semiconductor, Israel, 1997)
- NTSC
video circuit design (sync separator, automatic gain control, etc.) in
NMOS, (Micron Technology, Inc., 1994-1996)
- NMOS-only
PLL for a field emitting display to generate a pixel clock from NTSC
horizontal sync, (Micron Technology, Inc., 1995)
- Designed
the switched-capacitor pixel driver for a field-emitting display using 5 mm NMOS (Micron Technology, Inc.,
1994)
- 2 kV
pulse generator to drive Helmholz coils, (Lawrence Berkeley Labs, 1993-1994)
- Worked
on time-domain impulse radar circuits, (LLNL, 1993)
- Micro-channel
plate (MCP) drivers for high-speed photography, (E.G.& G. and LLNL, 1989-1993)
- Designed
all sorts of discriminators and triggering circuits for nuclear diagnostic
instrumentation, (E.G.& G. and
LLNL, 1986-1993)
- HV
sweep circuits for streak cameras and drivers for Pockel’s
cells used in femto- and pico-second
electro-optic instrumentation, (E.G.&
G. and LLNL, 1986-1993)
- Avalanche
and MOSFET transistor pulse generators for use in high-speed
instrumentation, (E.G.& G. and
LLNL, 1986-1993)
- CAMAC memory
system for storing CCD data operating at up to 100 MHz, (E.G.& G. and LLNL, 1986-1993)
- Battery
charger and back-up system for an SRAM memory system, (E.G.& G. and LLNL, 1989)
- Hybrid
(on alumina) integrated circuit vertical amplifier design for E.G.&G.’s
10 GHz TWT using HBTs supplied by TI, (E.G.&
G. and LLNL, 1989-1991)
- Design
of bit and frame-syncs (SerDes) for high-speed
(90, 180, and 720 Mb/s) communications using board-level ECL, (E.G.& G. and LLNL, 1988-1991)
- Camera
design using E.G.&G. Reticon CCDs, (E.G.& G. and LLNL, 1988-1991)
- Fiber-optic
transmitter and receiver design for 2 km serial links MM and SM fibers at
800 nm and 1.3 mm wavelengths, (E.G.& G. and LLNL, 1987-1991)
- Equalizer
design, DC restore, system design for high frequency analog and digital
signal transmission (electrical and optical), (E.G.& G. and LLNL, 1987-1991)
- Digital-to-analog
calibration system for calibrating ADCs in CCD imaging chips, (E.G.& G. and LLNL, 1986-1987)
- Design
of high-voltage pulse and ramp generators using planar triodes and krytrons, (E.G.&
G. and LLNL, 1986-1987)
- Battery-operated
tunnel diode pulse generator for checking compensation of oscilloscopes at
the Nevada Test Site, (E.G.& G.
and LLNL, 1985-1986)
- Primary
and secondary power system design, installation and troubleshooting
electric motors on mining equipment, (Reynolds
Electrical Engineering Company [REECo], 1985)
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