Simple
ReadOut
Integrated Circuit (ROIC) to Test Bumping and Bonding InGaAs
FPAs to CMOS
Shown below are images
of a simple chip designed and
laid out by Jake
Baker in
2010 for testing the process of bumping Aerius Photonics' Focal Plane
Arrays
(FPAs, here a small 4 by 4 FPA) to CMOS. The chips were fabricated in ON’s
C5
process through MOSIS
and are
1 mm square. Click images to enlarge.
Last
Updated Saturday, June 18, 2011