152. Baker, R. J., “Quantizing circuits having improved sensing," 10,658,018, May 19, 2020.
151. Baker, R. J., “Quantizing
circuits having improved sensing," 10,403,339,
September 3, 2019.
150. Baker, R. J.,
"Digital Filters with Memory," 10,366,744, July
30, 2019.
149. Baker, R. J., “Quantizing
circuits having improved sensing," 10,127,954, November
13, 2018.
148. Baker, R. J. and
Parkinson, W., "NMOS regulated voltage reference," 9,753,481, September
5, 2017.
147. Baker, R. J.,
"Digital Filters with Memory," 9,734,894, August
15, 2017.
146. Baker, R. J. and Keeth,
B., "Optical interconnect in high-speed memory systems," 9,697,883, July 4,
2017.
145. Baker, R.
J., “Comparators for delta-sigma modulators,” 9,641,193, May 2,
2017.
144. Baker, R. J., “Quantizing
circuits having improved sensing,” 9,449,664, September
20, 2016.
143. Baker, R. J., “Error
detection for multi-bit memory,” 9,336,084, May 10,
2016.
142. Baker, R. J. and Keeth, B., “Optical interconnect
in high-speed memory systems,” 9,299,423, March 29, 2016.
141. Baker, R. J., “Methods for sensing memory
elements in semiconductor devices,” 9,299,405, March 29,
2016.
140. Baker, R.
J., “Comparators for delta-sigma modulators,” 9,135,962, September
15, 2015.
139. Baker, R. J., “Resistive memory element
sensing using averaging,” 9,081,042, July 14,
2015.
138. Baker, R. J., “Digital Filters with Memory,”
9,070,469, June
30, 2015.
137. Baker, R. J., "Reference current sources,” 8,879,327,
November 4, 2014.
136. Baker, R. J.
and Beigel, K. D., “Multi-resistive integrated circuit memory,” 8,878,274, November
4, 2014.
135. Baker, R. J., “Methods for sensing memory
elements in semiconductor devices,” 8,854,899, October
7, 2014.
134. Baker, R. J.,
“Quantizing circuits with variable parameters,” 8,830,105, September
9, 2014.
133. Baker, R. J., “Integrators for delta-sigma
modulators,” 8,754,795,
June 17, 2014.
132. Baker, R. J.,
“Methods of quantizing signals using variable reference signals,” 8,717,220, May 6,
2014.
131. Baker, R. J. and Keeth, B., “Optical
interconnect in high-speed memory systems,” 8,712,249, April
29, 2014.
130. Baker, R. J., “Resistive memory
element sensing using averaging,” 8,711,605, April 29,
2014.
129. Baker, R. J., “Memory with correlated resistance,” 8,681,557, March 25, 2014.
128. Baker, R. J., “Reference current sources,” 8,675,413, March 18,
2014.
127. Baker, R. J.,
“Methods for sensing memory elements in semiconductor devices,” 8,582,375, November
12, 2013.
126. Linder, L. F.,
Renner, D., MacDougal, M., Geske, J., and Baker, R.
J., “Dual well read-out integrated circuit (ROIC),” 8,581,168, November
12, 2013.
125. Li, W., Schoenfeld, A., and Baker, R. J., “Method and apparatus
for providing symmetrical output data for a double data rate DRAM,” 8,516,292, August
20, 2013.
124. Baker, R. J., “Resistive memory element sensing using
averaging,” 8,441,834,
May 14, 2013.
123. Harvard, Q. I., Drost, R.
J., and Baker, R. J., "Increased DRAM-array throughput using inactive bitlines," 8,395,947, March 12,
2013.
122. Baker, R. J., “Memory with correlated resistance,” 8,289,772, October
16, 2012.
121. Lin, F. and Baker, R. J., “Phase splitter using
digital delay locked loops,” 8,218,708, July 10,
2012.
120. Baker, R. J., “Subtraction circuits and
digital-to-analog converters for semiconductor devices,” 8,194,477, June 5,
2012.
119. Baker, R. J., “Digital Filters for Semiconductor
Devices,” 8,149,646,
April 3, 2012.
118. Baker, R. J., “Error detection for multi-bit
memory,” 8,117,520,
February 14, 2012.
117. Baker, R. J., “Integrators for delta-sigma
modulators,” 8,102,295,
January 24, 2012.
116. Baker, R. J., “Devices including
analog-to-digital converters for internal data storage locations,” 8,098,180, January
17, 2012.
115. Baker, R. J. and Beigel, K. D., “Multi-resistive
integrated circuit memory,” 8,093,643, January
10, 2012.
114. Baker, R. J., “Quantizing circuits with variable
parameters,” 8,089,387,
January 3, 2012.
113. Baker, R. J., “Reference current sources,” 8,068,367, November
29, 2011.
112. Baker, R. J., “Methods of quantizing signals
using variable reference signals,” 8,068,046, November
29, 2011.
111. Baker, R. J., “Systems and devices including
memory with built-in self test and methods of making
using the same,” 8,042,012,
October 18, 2011.
110. Baker, R. J., “Memory with correlated
resistance,” 7,969,783,
June 28, 2011.
109. Baker, R. J. and Keeth, B., “Optical interconnect in
high-speed memory systems,” 7,941,056, May 10,
2011.
108. Baker, R. J.,
“K-delta-1-sigma modulator,” 7,916,054, March 29,
2011.
107. Li, W., Schoenfeld, A., and Baker, R. J., “Method and
apparatus for providing symmetrical output data for a double data rate DRAM,” 7,877,623, January
25, 2011.
106. Lin, F. and Baker, R. J., “Phase splitter using
digital delay locked loops,” 7,873,131, January
18, 2011.
105. Hush, G. and Baker, R. J., “Complementary bit PCRAM
sense amplifier and method of operation,” 7,869,249, January
11, 2011.
104. Baker, R. J., “Subtraction circuits and
digital-to-analog converters for semiconductor devices,” 7,839,703, November
23, 2010.
103. Baker, R. J., “Digital Filters with Memory,” 7,830,729, November
9, 2010.
102. Baker, R. J., “Systems and devices including memory
with built-in self test and methods of making using
the same,” 7,818,638,
October 19, 2010.
101. Baker, R. J., “Integrators for delta-sigma
modulators,” 7,817,073,
October 19, 2010.
100. Baker, R. J., “Digital filters for semiconductor
devices,” 7,768,868,
August 3, 2010.
99. Baker, R. J., “Quantizing circuits with
variable reference signals,” 7,733,262, June 8,
2010.
98. Baker, R. J., “Quantizing circuits for
semiconductor devices,” 7,667,632, February
23, 2010.
97. Baker,
R. J., and Beigel, K. D., “Multi-resistive integrated circuit memory,” 7,642,591, January
5, 2010.
96. Baker,
R. J., “Offset compensated sensing for a magnetic random access memory,” 7,616,474, November
10, 2009.
95. Baker, R. J., “Resistive memory element sensing
using averaging,” 7,577,044,
Aug. 18, 2009.
94. Baker, R. J., “Quantizing circuits with variable
parameters,” 7,538,702,
May 26, 2009.
93. Baker, R. J., “Method and system for reducing
mismatch between reference and intensity paths in analog to digital converters
in CMOS active pixel sensors,” 7,528,877, May 5,
2009.
92. Baker, R. J., “Method and system for reducing
mismatch between reference and intensity paths in analog to digital converters
in CMOS active pixel sensors,” 7,515,188, April 7,
2009.
91. Taylor, J. and Baker, R. J., “Method and
apparatus for sensing flash memory using delta-sigma modulation,” 7,495,964, February
24, 2009.
90. Baker, R. J., “Noise resistant small signal sensing
circuit for a memory device,” 7,489,575, February
10, 2009.
89. Baker, R. J., “Per column one-bit ADC for image
sensors,” 7,456,885,
November 25, 2008.
88. Staples, T. and Baker, R. J., “Input buffer
design using common-mode feedback,” 7,449,953, November
11, 2008.
87. Li, W., Schoenfeld, A., and Baker, R. J.,
“Method and apparatus for providing symmetrical output data for a double data
rate DRAM,” 7,421,607,
September 2, 2008.
86. Baker, R. J., “Methods for resistive memory
element sensing using averaging,” 7,372,717, May 13,
2008.
85. Taylor, J. and Baker, R. J., “Method and
apparatus for sensing flash memory using delta-sigma modulation,” 7,366,021, April 29,
2008.
84. Hush, G. and Baker, R. J., “Method of
operating a complementary bit resistance memory sensor and method of
operation,” 7,366,003,
April 29, 2008.
83. Baker, R. J., “Noise resistant small signal
sensing circuit for a memory device,” 7,330,390, February
12, 2008.
82. Baker, R. J., “Input and output buffers having
symmetrical operating characteristics and immunity from voltage variations,” 7,319,620, January
15, 2008.
81. Staples, T. and Baker, R. J., “Method and
apparatus providing input buffer design using common-mode feedback,” 7,310,018, December
18, 2007.
80. Baker, R. J., “Offset compensated sensing for a
magnetic random access memory,” 7,286,428, October
23, 2007.
79. Baker, R. J., and Cowles, T. B., “Method and
apparatus for reducing duty cycle distortion of an output signal,” 7,271,635, September
18, 2007.
78. Baker, R. J., and Cowles, T. B., “Method
and apparatus for reducing duty cycle distortion of an output signal,” 7,268,603, September
11, 2007.
77. Hush, G., Baker, R. J., and Moore, J., “Skewed
sense AMP for variable resistance memory sensing,” 7,251,177, July 31,
2007.
76. Hush, G. and Baker, R. J., “Method of operating
a complementary bit resistance memory sensor,” 7,242,603, July 10,
2007.
75. Li, W., Schoenfeld, A., and Baker, R. J.,
“Method and apparatus for providing symmetrical output data for a double data
rate DRAM,” 7,237,136,
June 26, 2007.
74. Moore, J. and Baker, R. J., “Rewrite prevention
in a variable resistance memory,” 7,224,632, May 29,
2007.
73. Baker, R. J., “Integrated charge sensing scheme
for resistive memories,” 7,151,698, December
19, 2006.
72. Baker, R. J., “Adjusting the frequency of an
oscillator for use in a resistive sense amp,” 7,151,689, December 19,
2006.
71. Baker, R. J., “Resistive memory element sensing
using averaging,” 7,133,307,
Nov. 7, 2006.
70. Lin, F. and Baker, R. J., “Phase detector for
all-digital phase locked and delay locked loops,” 7,123,525, October
17, 2006.
69. Baker, R. J. and Beigel, K. D., “Integrated
circuit memory with offset capacitor,” 7,109,545, September
19, 2006.
68. Baker, R. J., “Input and output buffers having
symmetrical operating characteristics and immunity from voltage variations,” 7,102,932, September
5, 2006.
67. Baker, R. J., “Noise resistant small signal
sensing circuit for a memory device,” 7,095,667, August
22, 2006.
66. Baker, R. J., “Offset compensated sensing
for a magnetic random access memory,” 7,082,045, July 25,
2006.
65. Baker, R. J., “System and method for
sensing data stored in a resistive memory element using one bit of a digital
count,” 7,009,901,
March 7, 2006.
64. Hush, G. and Baker, R. J., “Complementary bit
resistance memory sensor and method of operation,” 7,002,833, February
21, 2006.
63. Lin, F. and Baker, R. J., “Phase detector for
all-digital phase locked and delay locked loops,” 6,987,701, January
17, 2006.
62. Baker, R. J., “Adjusting the frequency of an
oscillator for use in a resistive sense amp,” 6,985,375, January
10, 2006.
61. Baker, R. J., “Method for reducing power
consumption when sensing a resistive memory,” 6,954,392, October
11, 2005.
60. Baker, R. J., “Noise resistant small signal
sensing circuit for a memory device,” 6,954,391, October
11, 2005.
59. Baker, R. J., “Noise resistant small signal
sensing circuit for a memory device,” 6,954,390, October
11, 2005.
58. Lin, F. and Baker, R. J., “Phase splitter using digital
delay locked loops,” 6,950,487,
September 27, 2005.
57. Baker, R. J., “Method and apparatus for
measuring current as in sensing a memory cell,” 6,930,942, August
16, 2005.
56. Baker, R. J., “Offset compensated sensing
for a magnetic random access memory,” 6,917,534, July 12,
2005.
55. Baker, R. J., “Dual loop sensing scheme for
resistive memory elements,” 6,914,838, July 5,
2005.
54. Baker, R. J., “High speed low power input
buffer,” 6,914,454,
July 5, 2005.
53. Baker, R. J., and Beigel, K. D., “Method for
stabilizing or offsetting voltage in an integrated circuit,” 6,913,966, July 5,
2005.
52. Moore, J. and Baker, R. J., “PCRAM rewrite
prevention,” 6,909,656,
June 21, 2005.
51. Baker, R. J., “Integrated charge sensing scheme
for resistive memories,” 6,901,020, May 31,
2005.
50. Hush, G., Baker, R. J., and Moore, J., “Skewed
sense AMP for variable resistance memory sensing,” 6,888,771, May 3,
2005.
49. Baker, R. J., “Method for reducing power
consumption when sensing a resistive memory,” 6,885,580, April 26,
2005.
48. Moore, J. and Baker, R. J., “PCRAM rewrite
prevention,” 6,882,578,
April 19, 2005.
47. Baker, R. J., “Integrated charge sensing scheme
for resistive memories,” 6,870,784, March 22,
2005.
46. Baker, R. J., “Sensing method and apparatus
for resistive memory device,” 6,859,383, February
22, 2005.
45. Baker, R. J., “Noise resistant small signal
sensing circuit for a memory device,” 6,856,564, February
15, 2005.
44. Baker, R. J., “Offset compensated sensing
for a magnetic random access memory,” 6,856,532, February
15, 2005.
43. Baker, R. J., “Dual loop sensing scheme for
resistive memory elements,” 6,829,188, Dec. 7,
2004.
42. Baker, R. J., “Noise resistant small signal
sensing circuit for a memory device,” 6,826,102, Nov. 30,
2004.
41. Baker, R. J., “Resistive memory element
sensing using averaging,” 6,822,892, Nov. 23,
2004.
40. Baker, R. J., “System and method for
sensing data stored in a resistive memory element using one bit of a digital
count,” 6,813,208,
Nov. 2, 2004.
39. Baker, R. J., “Wordline driven method for
sensing data in a resistive memory array,” 6,809,981, Oct. 26,
2004.
38. Baker, R. J., “Noise resistant small signal
sensing circuit for a memory device,” 6,798,705, Sept. 28,
2004.
37. Baker, R. J., “Methods and apparatus for
measuring current as in sensing a memory cell,” 6,795,359, Sept. 21,
2004.
36. Hush, G. and Baker, R. J., “Complementary
bit PCRAM sense amplifier and method of operation,” 6,791,859, Sept. 14,
2004.
35. Baker, R. J., “Method and apparatus for
sensing resistance values of memory cells,” 6,785,156, August
31, 2004.
34. Lin, F. and Baker, R. J., “Phase detector
for all-digital phase locked and delay locked loops,” 6,779,126, August
17, 2004.
33. Baker, R. J., and Lin, F. "Digital
dual-loop DLL design using coarse and fine loops," 6,774,690, August
10, 2004.
32. Hush, G., Baker, R. J., and Voshell, T.,
“Producing walking one pattern in shift register,” 6,771,249, August 3,
2004.
31. Baker, R. J., “Sensing method and apparatus for
resistance memory device,” 6,741,490, May 25,
2004.
30. Li, W., Schoenfeld, A., and Baker, R. J.,
“Method and apparatus for providing symmetrical output data for a double data
rate DRAM,” 6,704,881,
March 9, 2004.
29 Baker, R. J., “Method and system for
writing data in an MRAM memory device,” 6,687,179, February
3, 2004.
28. Baker, R. J., “High speed digital signal buffer
and method,” 6,683,475,
January 27, 2004.
27. Baker, R. J., “High speed low power input
buffer,” 6,600,343,
July 29, 2003.
26. Baker, R. J., “Offset compensated sensing for
magnetic random access memory,” 6,597,600, July 22,
2003.
25. Baker, R. J., “Sensing method and apparatus for
resistive memory device,” 6,577,525, June 10,
2003.
24. Baker, R. J., “Method and apparatus for
sensing resistance values of memory cells,” 6,567,297, May 20,
2003.
23. Baker, R. J., “High-speed digital signal
buffer and method,” 6,538,473,
March 25, 2003.
22. Baker, R. J. and Beigel, K. D.,
"Electronic device with interleaved portions for use in integrated
circuits," 6,509,245,
January 21, 2003.
21. Baker, R. J., "Resistive memory
element sensing using averaging," 6,504,750, January
7, 2003.
20. Baker, R. J., "High-speed digital
signal buffer and method," 6,483,347, November
19, 2002.
19. Baker, R. J., and Lin, F., "Digital
dual-loop DLL design using coarse and fine loops," 6,445,231, September
3, 2002.
18. Baker, R. J., "Method and apparatus for
receiving synchronous data," 6,424,684, July 23,
2002.
17. Baker, R. J. and Beigel, K. D.,
"Comb-shaped capacitor for use in integrated circuits," 6,410,955, June 25,
2002.
16. Baker, R. J., "High-speed,
low-power input buffer," 6,407,588, June 18,
2002.
15. Miller, J., Schoenfeld, A., Ma, M., and
Baker, R. J., "Method and apparatus for improving the performance of
digital delay locked loop circuits," 6,316,976, Nov. 13,
2001.
14. Keeth, B. and Baker, R. J., "Low skew
differential receiver with disable feature," 6,256,234, July 3,
2001.
13. Keeth, B. and Baker, R. J., "Low skew
differential receiver with disable feature," 6,104,209, August
15, 2000.
12. Miller, J., Schoenfeld, A., Ma, M., and
Baker, R. J., "Method and apparatus for improving the performance of
digital delay locked loop circuits," 6,069,506, May 30,
2000.
11. Keeth, B. and Baker, R. J., "Low skew
differential receiver with disable feature," 6,026,051,
February 15, 2000.
10. Baker, R. J., and Manning, T. A., "Method
and apparatus for adaptively adjusting the timing of a clock signal used to
latch digital signals, and memory device using same," 6,026,050, February
15, 2000.
9. Baker, R. J., and Manning, T. A.,
"Method and apparatus for adaptively adjusting the timing of a clock
signal used to latch digital signals, and memory device using same," 5,953,284, September
14, 1999.
8. Baker, R. J.,
"Fully-differential amplifier," 5,953,276, September
14, 1999.
7. Hush, G., Baker, R. J., and Voshell,
T., "Timing Control for a Matrixed Scanned Array," 5,909,201, June 1,
1999.
6. Hush, G. and Baker, R. J.,
"Field emission display having pulsed capacitance current control," 5,894,293, April 13,
1999.
5. Baker, R. J., "Adaptively biased
voltage regulator and operating method," 5,874,830, February
23, 1999.
4. Hush, G. Baker, R. J., and Voshell,
T., "Serial to Parallel Conversion with a Phase-Locked Loop," 5,818,365, October
1, 1998
3. Hush, G., Baker, R. J., and Voshell,
T., "Timing Control for a Matrixed Scanned Array," 5,638,085, June 10,
1997.
2. Wilson, A. J., Baker, R. J., and
Schoenfeld, A., "Waveshaping circuit generating two rising slopes for a
sense amplifier pulldown device," 5,614,856, March 25,
1997.
1. Hush, G., Baker, R. J., and Voshell, T.,
"Serial to Parallel Conversion with a PLL," 5,598,156, January
28, 1997.