TIA and Various Structures Test Chip

Project Members:

Gonzalo Arteaga (arteag1@unlv.nevada.edu)  

R. Jacob Baker (rjacobbaker@gmail.com)  

Tyler Ferreira (ferret1@unlv.nevada.edu)

Dane Gentry (gentryd2@unlv.nevada.edu) 

James Mellott (mellott@unlv.nevada.edu)

Eric Monahan (monahan@unlv.nevada.edu)
Sachin P. Namboodiri (puruss1@unlv.nevada.edu)

Angsuman Roy (angsumanroy@gmail.com)

Vikas Vinayaka (vinayaka@unlv.nevada.edu)

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TIA Test Chip

This test chip was designed in 2018 and fabricated using the ams 0.35um SiGe (S35) process and consists of the following circuitry:

· 16 Stage FTD (Fast Transient Digitizer)

· 2 simple TIA’s

· Fully differential TIA

· 3.3V Op-Amp

· Comparator

· 2 Band Gaps

· 24u Area NPN transistor

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Pad Frame/Key

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Pin Table

Pin #	Name on Pad Key	Pin Description
1	VDD	VDD Connection for all on chip devices (except Op-Amp)
2	GND	Ground connection for all on chip devices
3	FTD-A3	FTD A3 decoder input
4	FTD-A2	FTD A2 decoder input
5	FTD-A1	FTD A1 decoder input
6	FTD-A0	FTD A0 decoder input
7	FTD-VE	FTD VE decoder input
8	FTD-OUT	FTD output to 20K off chip resistor
9	FTD-Analog In	FTD analog input to be stored
10	FTD-Trigger In	Trigger input to start FTD capture
11	FTD-Trigger Out	FTD trigger out to determine capture window
12	FTD-Vinvco	FTD voltage controlled input to vary FTD stage delay
13	FTD-Vres	Bias generation resister to set current in current starved inverters
14	TIA8-out2	Output also referred to as pad 2 in schematic
15	TIA8-in1	Input also referred to as pad 1 in schematic
16	TIA8-bres3	Bias resistor from off chip, also referred to as pad 3 in schematic
17	TIAV-Vinp	Plus input for differential TIA
18	TIAV-Vinm	Minus input for differential TIA
19	TIAV-Vo	Output for Vikas’ TIA
20	GND	Ground connection for all on chip devices
21	VDD	VDD Connection for all on chip devices (except Op-Amp)
22	TIA10-out2	Output also referred to as pad 2 in schematic
23	TIA10-in1	Input also referred to as pad 1 in schematic
24	TIA10-bres3	Bias resistor from off chip, also referred to as pad 3 in schematic
25	Opamp-V-	3.3V op-amp differential V- input
26	Opamp-V+	3.3V op-amp differential V+ input
27	Opamp-Vout	3.3V op-amp differential Vout
28	Comparator	Comparator output
29	Comparator	Comparator Clock input
30	Comparator	Comparator outputm
31	Comparator	Comparator outputp
32	Comparator	Comparator inp
33	Comparator	Comparator inm
34	Comparator	Comparator outi
35	BandGap1-Out	Band Gap output
36	*BandGap-VDD*	*Band Gap VDD input for Band Gap 1 and 2, and Collector of NPN*
37	Opamp-VDD	3.3V VDD connection for Op-amp
38	NPN-Emitter	24u area NPN Emitter
39	NPN-Base	24u area NPN Base
40	BandGap2-Out	5u x 5u Full Guard Ring APD – Anode (A)

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Pin Tables

(Global VDD pins 1,21 Global GND pins 2,20)

24u area NPN

Component	Base	Emitter	Collector
24u Area NPN BJT	Pin 39	Pin 38	Pin 36

FTD

Component	Trigger In	Trigger Out	Analog In	Out	Vinvco	Bias Resistor
FTD	Pin 10	Pin 11	Pin 9	Pin 8	Pin 12	Pin 13

FTD-Decoder

Component	VE	A0	A1	A2	A3
Decoder	Pin 7	Pin 6	Pin 5	Pin 4	Pin 3

TIA 8

Component	Bias R	Input	Out
TIA	Pin 16	Pin 15	Pin 14

TIA 10

Component	Bias R	Input	Out
TIA	Pin 24	Pin 23	Pin 22

Vikas’ TIA

Component	Vinp	Vinm	Vout
TIA	Pin 17	Pin 18	Pin 19

Op-Amp

Component	V-	V+	Vout	VDD
Op-Amp	Pin 25	Pin 26	Pin 27	Pin 37

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