The Electric VLSI Design
System
Dr. Steven M. Rubin leads the development of Electric in the VLSI Research Group at Oracle, Inc.
- The Electric VLSI Design System – free and powerful CAD system for chip design (schematics, layout, DRC, LVS, ERC, etc.) that runs on any platform (Unix, Linux, Mac, Windows).
- The Google group for Electric is located at http://groups.google.com/group/electricvlsi. Also see the Electric Users around the World (map)
- Electric’s history at Wikipedia.org.
- An online user’s manual with tutorial is found here and examples are found here.
- Tutorials and videos illustrating the use of Electric are seen here.
- Labs using Electric are found in 8-bit MIPS microprocessor (from Prof. Gupta at Villanova U.)
- Very helpful information from Kazzz is found in: Eclipse-GNU-Electric.ppt and EditTechnology-GNU-Electric.ppt
- Detailed information on installing and using Electric with add-ons (e.g., SPICE) is found here.
Quick install: ensure Java is installed (go to java.com) and save electricBinary-8.11.jar to your computer (e.g., the Desktop).
- Double clicking on this saved jar file starts Electric in Windows using 64 MB of memory (see here for how to increase memory allocation, very important if doing simulations or large designs).
- In Linux/Unix open a terminal window, navigate to where you saved the jar file, and enter: java -Xmx512m -jar electricBinary-8.11.jar & to start Electric with 512 MB of memory.
- For the Mac, double clicking on the saved jar file should start Electric. If not, use the Linux/Unix command-line command seen above in a xterm.
- Examples for the C5 process for fabrication through MOSIS are found in (right click to “Save As”):
o MOSIS_SUBM_PADS_C5.jelib and INFO_SUBM_PADS_C5.pdf (analog and digital pads with test chips)
- Open these libraries after you start Electric (File -> Open Library). Save C5_models.txt for LTspice simulations.
- Hundreds of examples are found on the CMOS books' webpages!
- Tutorials from CMOSedu.com are found here.
- Untested analog and digital pads for TSMC’s CL018 (180 nm, lambda = 90 nm) CMOS process using the MOSIS DEEP rules are found in MOSIS_DEEP_PADS_CL018.zip
Return to:
CMOS Circuit Design, Layout, and Simulation
CMOS Mixed-Signal Circuit Design