Phase-Locked Loop with 560 MHz output
Below is the layout of a test PLL designed during the summer of 1998 (Amkor
wafer fabrication services, Boise, Idaho) for clock generation using a .35 um
process.
Below is the layout of a test PLL designed during the summer of 1998 (Amkor
wafer fabrication services, Boise, Idaho) for clock generation using a .35 um
process.