Below is a schematic of an 11-bit DAC (7-bits monontonic) designed by RJB for a power line communications chip designed by ITRAN communications. The process used is Tower Semiconductors 0.35 um process. The chip uses the power op-amp discussed here. This DAC uses a novel R-2R architecture that allows the op-amp inputs to remain at VDD/2 while allowing the output of the DAC to reach from ground to VDD.