Video Lectures to support the textbook CMOS Mixed-Signal Circuit Design

Videos to support the Textbook CMOS Mixed–Signal Circuit Design

Chapter 1 – Signals, Filters, and Tools

1.1 Sinusoidal Signals – 1.1.1 The Pendulum Analogy and 1.1.2 The Complex (z–) Plane – ch1_msd_1_1_video (56:26), ch1_msd_1_1_notes.pdf, and ch1_msd_1_1.zip
1.2 Comb Filters – 1.2.1 The Digital Comb Filter, 1.2.2 The Digital Differentiator, 1.2.3 An Intuitive Discussion of the z–Plane, 1.2.4 Comb Filters with Multiple Delay Elements, and 1.2.5 The Digital Integrator – ch1_msd_1_2_video (71:22), ch1_msd_1_2_notes.pdf, and ch1_msd_1_2.zip

Chapter 2 – Sampling and Aliasing

2.1.part1 Sampling – 2.1.1 Impulse Sampling and 2.1.2 Decimation – ch2_msd_2_1_p1_video (56:24) and ch2_msd_2_1_p1_notes.pdf
2.1.part2 Sampling – 2.1.3 The Sample–and–Hold (S/H), and 2.1.4 The Track–and–Hold (T/H) – ch2_msd_2_1_p2_video (54:32), ch2_msd_2_1_p2_notes.pdf, and ch2_msd_2_1_p2.zip
2.1.part3 Sampling – 2.1.5 Interpolation – ch2_msd_2_1_p3_video (59:58) and ch2_msd_2_1_p3_notes.pdf
2.1.part4 Sampling – 2.1.6 K–path Sampling – ch2_msd_2_1_p4_video (71:17), ch2_msd_2_1_p4_notes.pdf, and ch2_msd_2_1_p4.zip
2.2.part1 Circuits – 2.2.1 Implementing the S/H – ch2_msd_2_2_p1_video (65:32), ch2_msd_2_2_p1_notes.pdf, and ch2_msd_2_2_p1.zip

Chapter 3 – Analog Filters

3.1.part1 Integrator Building Blocks – 3.1.1 Lowpass Filters and 3.1.2 Active–RC Integrators – ch3_msd_3_1_p1_video (61:06) and ch3_msd_3_1_p1_notes.pdf
3.1.part2 Integrator Building Blocks – 3.1.3 MOSFET–C Integrators, 3.1.4 gm–C (Transconductor–C) Integrators, and 3.1.5 Discrete–Time Integrators – ch3_msd_3_1_p2_video (55:58) and ch3_msd_3_1_p2_notes.pdf
3.2.part1 Filtering Topologies – 3.2.1 The Bilinear Transfer Function and 3.2.2 The Biquadratic Transfer Function – ch3_msd_3_2_p1_video (61:49) and ch3_msd_3_2_p1_notes.pdf
3.2.part2 Filtering Topologies – 3.2.2 The Biquadratic Transfer Function – ch3_msd_3_2_p2_video (45:54) and ch3_msd_3_2_p2_notes.pdf

Chapter 4 – Digital Filters

4.1 SPICE Models for DACs and ADCs – 4.1.1 The Ideal DAC, 4.1.2 The Ideal ADC, 4.1.3 Number Representation, 4.2 Sinc–Shaped Digital Filters, and 4.2.1 The Counter – ch4_msd_4_1_video (66:54), ch4_msd_4_1_notes.pdf, and ch4_msd_4_1.zip
4.2 Sinc–Shaped Digital Filters – 4.2.2 Lowpass Sinc Filters, 4.2.3 Bandpass and Highpass Sinc Filters, and 4.2.4 Interpolation using Sinc Filters – ch4_msd_4_2_video (75:31), ch4_msd_4_2_notes.pdf, and ch4_msd_4_2.zip
4.2.5 Decimation using Sinc Filters – ch4_msd_4_2_p2_video (41:05), ch4_msd_4_2_p2_notes.pdf, and ch4_msd_4_2_p2.zip

Chapter 5 – Data Converter SNR

5.1 Quantization noise – 5.1.1 Viewing the Quantization Noise Spectrum Using Simulations and Quantization Noise Voltage Spectral Density – ch5_msd_5_1_video (28:35), ch5_msd_5_1_notes.pdf, and ch5_msd_5_1.zip
5.2 Signal–to–Noise Ratio (SNR) – 5.2.1 Clock Jitter and 5.2.2 A Tool: The Spectral Density – ch5_msd_5_2_video (63:23), ch5_msd_5_2_notes.pdf, and ch5_msd_5_2.zip
5.3 Improving SNR using Averaging – 5.3.1 Using Averaging to Improve SNR, 5.3.2 Linearity Requirements, 5.3.3 Adding a Noise Dither, 5.3.4 Jitter, and 5.3.5 Anti–Aliasing Filter – ch5_msd_5_3_video (67:48), ch5_msd_5_3_notes.pdf, and ch5_msd_5_3.zip
5.4 Using Feedback to Improve SNR – ch5_msd_5_4_video (17:35), ch5_msd_5_4_notes.pdf

Chapter 6 – Data Converter Design Basics

6.1 Passive Noise–Shaping – ch6_msd_6_1_video (38:51), ch6_msd_6_1_notes.pdf, and ch6_msd_6_1.zip
6.1 Passive Noise–Shaping – 6.1.1 Signal–to–Noise Ratio and 6.1.2 Decimating and Filtering the Modulator's Output – ch6_msd_6_1_p1_video (30:51), ch6_msd_6_1_p1_notes.pdf, and ch6_msd_6_1_p1.zip
6.1 Passive Noise–Shaping – 6.1.3 Offset, Matching, and Linearity – ch6_msd_6_1_p2_video (54:30), ch6_msd_6_1_p2_notes.pdf, and ch6_msd_6_1_p2.zip
6.2 Improving SNR and Linearity – 6.2.1 Second–Order Passive Noise–Shaping and 6.2.2 Passive Noise–Shaping Using Switched–Capacitors – ch6_msd_6_2_p1_video (68:39), ch6_msd_6_2_p1_notes.pdf, and ch6_msd_6_2_p1.zip
6.3 Improving SNR and Linearity – 6.2.3 Increasing SNR using K–Paths and 6.2.4 Improving Linearity Using an Active Circuit – ch6_msd_6_2_p2_video (61:55), ch6_msd_6_2_p2_notes.pdf, and ch6_msd_6_2_p2.zip

Chapter 7 – Noise–Shaping Data Converters

7.1 First–Order Noise Shaping – 7.1.1 Modulation Noise in First–Order NS Modulators, 7.1.2 RMS Quantization Noise in a First–Order Modulator, and 7.1.3 Decimating and Filtering the Output of a NS Modulator – ch7_msd_7_1_p1_video (61:15), ch7_msd_7_1_p1_notes.pdf, and ch7_msd_7_1_p1.zip
7.1.4 Pattern Noise from DC Inputs (Limit Cycle Oscillations), 7.1.5 Integrator and Forward Modulator Gain, 7.1.6 Comparator Gain, Offset, Noise, and Hysteresis, and, 7.1.7 Op–Amp Gain (Integrator Leakage) – ch7_msd_7_1_p2_video (70:44), ch7_msd_7_1_p2_notes.pdf, and ch7_msd_7_1_p2.zip
7.1.8 Op–Amp Settling Time, 7.1.9 Op–Amp Offset, 7.1.10 Op–Amp Input–Referred Noise, and 7.1.11 Practical Implementation of the First–Order NS Modulator – ch7_msd_7_1_p3_video (65:32), ch7_msd_7_1_p3_notes.pdf, and ch7_msd_7_1_p3.zip
7.2 Second–Order Noise Shaping – 7.2.1 Second–Order Modulator Topology, 7.2.2 Integrator Gain, and 7.2.3 Selecting Modulator (Integrator) Gains – ch7_msd_7_2_p1_video (69:37), ch7_msd_7_2_p1_notes.pdf, and ch7_msd_7_2_p1.zip
7.3 Noise–Shaping Topologies – 7.3.1 Higher–Order Modulators, 7.3.2 Filtering the Output of an Mth–Order NS Modulator, 7.3.3 Implementing Higher–Order, Single–Stage Modulators, 7.3.4 Multi–Bit Modulators, and 7.3.5 Error Feedback – ch7_msd_7_3_p1_video (62:36) and ch7_msd_7_3_p1_notes.pdf
7.3.6 Cascaded Modulators – ch7_msd_7_3_p2_video (16:05), ch7_msd_7_3_p2_notes.pdf, and ch7_msd_7_3_p2.zip

Chapter 8 – Bandpass Data Converters

8.1 Continuous–Time Bandpass Noise–Shaping – 8.1.1 Passive–Component Bandpass Modulators, 8.1.2 Active–Component Bandpass Modulators, and 8.1.3 Modulators for Conversion at Radio Frequencies – ch8_msd_8_1_video (45:59), ch8_msd_8_1_notes.pdf, and ch8_msd_8_1.zip
8.2 Switched–Capacitor Bandpass Noise–Shaping – 8.2.1 Switched–Capacitor Resonators, 8.2.2 Second–Order Modulators, 8.2.3 Fourth–Order Modulators, and 8.2.4 Digital I/Q Extraction to Baseband – ch8_msd_8_2_video (35:22), ch8_msd_8_2_notes.pdf, and ch8_msd_8_2.zip

Chapter 9 – A High–Speed Data Converter

9.1 The Topology (of a high–speed data converter) – 9.1.1 Clock Signals, 9.1.2 Implementation, 9.1.3 Filtering, 9.1.4 Discussion, and 9.1.5 Understanding the Clock Signals – ch9_msd_9_1_video (43:54), ch9_msd_9_1_notes.pdf, and ch9_msd_9_1.zip

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