EE 421L Digital Electronics Lab
Lab1 - Laboratory introduction & familiarizing myself with Cadence
Lab2 - Design of a 10-bit digital-to-analog converter (DAC)
Lab3 - Layout of a 10-bit DAC
Lab4 - IV characteristics and layout of NMOS and PMOS devices in ON's C5 process
Lab5 - Design, layout, and simulation of a CMOS inverter
Lab6 - Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder
Lab7 - Using buses and arrays in the design of word inverters, muxes, and high–speed adders
Lab8 - Generating a test chip layout for submission to MOSIS for fabrication
Project - Design and layout of an even parity checking circuit
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Fall 2017 webpage