EE 421L Digital Integrated Circuit Design Laboratory
Fall 2016, University of Nevada, Las Vegas

 

Student lab reports are found here.

  

Current grades are located here.

   
Lab Chip Projects
Chip1_f16 – Federico, Staford, Kristal
Chip2_f16 – Charlie, Ulises, Antanasia
Chip3_f16 – Ja, Zach, Carlos
Chip4_f16 – Chandon, James G., Kyle
Chip5_f16 – Eric, James M., Issac
Chip6_f16 – Michael, Martin, Billy, Dominique
Chip7_f16 – Sharyn, Raheel, Tyler F., Tyler H.
 

First half of the project (just the detector schematics, no layout), of your design and an html report detailing operation (including simulations), is due at the beginning of lab on Nov. 16. 

Your detector circuit should show various inputs to verify it works

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu.  

Dr. Baker will go over your designs with you, including running simulations, when lab meets on Nov. 16.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 30.

Again, I will meet with you on Nov. 30 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.  

Ensure that there is a link on your project report webpage to your zipped design directory.  

 
Project – design a circuit that takes a serial input and detects (outputs a high logic signal called detect) the sequence 101011
The inputs to your circuit are clk and in
Make sure that the output of your design, detect, is buffered before connecting to a pad
 
November 23 – Lab8 – Generating a test chip layout for submission to MOSIS for fabrication, due December 7
October 26 – Lab7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders, due November 16
October 5 – Lab6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder, due October 26
September 28 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 5  
September 21 – Lab4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process, due September 28
September 14 – Lab3 – Layout of a 10–bit DAC, due September 21  
September 7 – Lab2 – Design of a 10–bit digital–to–analog converter (DAC), due September 14  
August 31 – Lab1 – Laboratory introduction, generating/posting html lab reports, installing and using Cadence, due September 7  
   

Instructor: R. Jacob Baker

Lab Assistant: Claire Tsagkari  
Time: Wednesday from 11:30 to 2:15 PM

Course dates: Wednesday, August 31 to Wednesday, December 7

Location: TBE B–350

Holidays: none

Course content – Laboratory based analysis and design of digital and computer electronic systems.

Credits: 1

Corequisite: EE 421; Prerequisite: EE 320L

 

Grading
30% Quizzes
40% Lab Reports

30% Project
 

Policies 

  • Unlike the lectures, laptops can be used during the lab. Please bring your laptop with you to lab!
  • If a quiz is open book then only the course textbook can be used (no ebooks, Kindle, Nook, etc., older/international editions, or photocopies).
  • No late work accepted. Regularly being tardy for labs, leaving in the middle of labs, or leaving early is unacceptable without consent of the instructor.
  • Cheating or plagiarism will result in an automatic F grade in the lab
  • Questions for the instructor (only) should be asked in person (not via email).
  

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