EE 421L Digital Integrated Circuit Design Laboratory
Fall 2017, University of Nevada, Las Vegas
Student lab reports are found here.
grades are located here.
Project (not a group effort, each student will turn in their own project) – design an even parity checking circuit having a 9-bit input word, 8-bits data and 1-bit parity, that outputs a 1 (0) when the even parity check is valid (invalid)
The inputs to your circuit are D0-D7, P and the output is check
Make sure that the output of your design, check, is buffered before connecting to a pad
half of the project (just the parity checker schematics, no
layout), of your design and an html report detailing operation
(including simulations), is due at the beginning of lab on Nov. 15.
Your parity checker design should show various inputs to verify it works
Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu.
Dr. Baker will go over your design with you, including running simulations, when lab meets on Nov. 15.
Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 22.
Dr. Baker will meet with you on Nov. 22 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.
Ensure that there is a link on your project report webpage to your zipped design directory.
Instructor: R. Jacob Baker (see office hours at this link)
Lab Assistant: Sachin Namboodiri
Time: Wednesday from 11:30 to 2:15 PM
Course dates: Wednesday, August 30 to Wednesday, December 6
Location: TBE B–350
Course content – Laboratory based analysis and design of digital and computer electronic systems.
Corequisite: EE 421; Prerequisite: EE 320L
40% Lab Reports