EE 421L Digital Integrated Circuit Design Laboratory
Fall 2017, University of Nevada, Las Vegas


Student lab reports are found here.


Current grades are located here.

Lab Chips
Chip1_f17 – Reiner, John, Angel  
Chip2_f17 – Brett, Trevor, Aaron
Chip3_f17 – Gonzalo, Byron, Mario
Chip4_f17 – Jeremy, Preston, Miguel
Chip5_f17 – Desi, Jeeno, Junho  
Chip6_f17 – Andy, Dominic, Prachi
Chip7_f17 – Adam, Surafel, Ethan

Project (not a group effort, each student will turn in their own project) – design an even parity checking circuit having a 9-bit input word, 8-bits data and 1-bit parity, that outputs a 1 (0) when the even parity check is valid (invalid)  

The inputs to your circuit are D0-D7, P and the output is check  

Make sure that the output of your design, check, is buffered before connecting to a pad

First half of the project (just the parity checker schematics, no layout), of your design and an html report detailing operation (including simulations), is due at the beginning of lab on Nov. 15.  

Your parity checker design should show various inputs to verify it works

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu.  

Dr. Baker will go over your design with you, including running simulations, when lab meets on Nov. 15.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 22.

Dr. Baker will meet with you on Nov. 22 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.  

Ensure that there is a link on your project report webpage to your zipped design directory.  

November 29 – Lab8 – Generating a test chip layout for submission to MOSIS for fabrication, due December 6
October 25 – Lab7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders, due November 8
October 11 – Lab6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder, due October 25
September 27 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 11   
September 20 – Lab4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process, due September 27 
mber 13 – Lab3 – Layout of a 
10–bit DAC, due September 20  
September 6 – Lab2 – Design of a 10–bit digital–to–analog converter (DAC), due September 13  
August 30 – Lab1 – Laboratory introduction, generating/posting html lab reports, installing and using Cadence, due September 6  
Watch the Lab Safety Training video and review the Lab Rules & Regulations here  

Instructor: R. Jacob Baker (see office hours at this link)

Lab Assistant: Sachin Namboodiri 
Time: Wednesday from 11:30 to 2:15 PM

Course dates: Wednesday, August 30 to Wednesday, December 6

Location: TBE B–350

Holidays: none

Course contentLaboratory based analysis and design of digital and computer electronic systems.

Credits: 1

Corequisite: EE 421; Prerequisite: EE 320L


30% Quizzes
40% Lab Reports

30% Project


  • Unlike the lectures, laptops can be used during the lab. Please bring your laptop with you to lab!
  • If a quiz is open book then only the course textbook can be used (no ebooks, Kindle, Nook, etc., older/international editions, or photocopies).
  • No late work accepted. Regularly being tardy for labs, leaving in the middle of labs, or leaving early is unacceptable without consent of the instructor.
  • Cheating or plagiarism will result in an automatic F grade in the lab
  • Questions for the instructor (only) should be asked in person (not via email).