Lab 08 - EE 421L 

12/06/2017

Generating a test chip layout for submission to MOSIS for fabrication

Junho Bae

baej8@unlv.nevada.edu

Desi Battle

battled@unlv.nevada.edu

Jeeno Doria

doriaj3@unlv.nevada.edu

(VDD = 5 V)

This Chip contains the following:

1. A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
2. NAND gate using 6u/0.6u NMOS and PMOS
3. NOR gate using 6u/0.6u NMOS and PMOS
4. An inverter made with a 6u/0.6u NMOS and a 12u/0.6u PMOS
5. Transistors, both PMOS and NMOS, measuring 6u/0.6u
6. A 25k resistor implemented using the n-well
7. A voltage divider using the 25k resistor laid out above and a 10k resistor
8. An even partiy checker 9-bit input word (8-bits data & 1 bit parity), 1 output

        

         

Chip Schematic	Chip Layout
DRC	LVS

           
Drain: Pin<18>                                                                                           

NOR 

Inputs: Pin<7> and Pin<8>
VDD: Pin<10>
Output: Pin<9>

NAND

Inputs: Pin<3> and Pin<4>
VDD: Pin<6>
Output: pin<5> 

Test Instructions:
Connect Pin<6> to VDD
Connect Pin<3> and Pin<4> to all 4 possible combinations of 0,VDD and observe
Pin<5> is correct
 
    

Inverter

Inputs: Pin<21>
VDD: Pin<23>
Output: Pin<22> 

Test Instructions:
Connect Pin<23> to VDD
Apply square wave to Pin<21> and observe inverted output wave
 
   

VDD: Pin<2>
Output: Pin<1>

Test Instructions:
Connect Pin<2> to VDD
Connect a 20pF(max)  capacitor between Pin<1> and Pin<20> (ground
Observe output oscillates with

   

Voltage Divider

Input: Pin<11>
Output: Pin<12> 

Test Instructions:
Connect Pin<11> to known voltage
measure Pin<12> (Out = 0.7In)
 
   

Even Parity Checker

Inputs: Pin<24:31> (Data) and Pin<32> Parity(P)
Output (check): Pin<33>
VDD: pin<34>

Even Parity Checker operation

Test Instructions:
Supply VDD (5V) to pin<34>
Ensure all input pins are either grounded or tied to VDD and observe output is correct

No Connection

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