Digital IC Design - ECE 421L 

University of Nevada, Las Vegas
Fall 2023

Instructor: R. Jacob Baker, PhD, PE
Authored: Leonardo Ledesma
UNLV Email : ledesl1@unlv.nevada.edu

Digital IC Design Labs

Lab 1 - Introduction to Cadence and HTML Formatting

 Lab 2 - Design and Simulation of 10-bit DAC

 Lab 3 - Layout of 10-bit DAC in C5 Process

 Lab 4 - Layout and IV Characteristics of NMOS and PMOS Devices

 Lab 5 - Design, Layout and Simulation of CMOS Inverter

 Lab 6 - Design Layout and Simulation of CMOS NAND Gate, XOR Gate, and Full-Adder

 Lab 7 - Word Inverter, Muxes, and High Speed Adder using Buses and Arrays

 Lab 8 - MOSIS Test Chip Layout for Fabrication

  Lab Project - Non-Inverting Buffer   

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