Figure 1: 10K resistor layout
Figure 2: 10K resistor extracted view verifying correct value
Moving on the 10K resistor will be used to create a single bit DAC circuit which will then be instantiated 10 times to form the 10-bit DAC layout. Below is a single bit formation using 3 of the previously shown 10K resistors. Care was taken to be sure the resistors were stacked in alignment of the x-axis to make the layout of the 10-bit DAC easier.
Figure 3: Layout of single bit DAC
The single bit layout is then ran through a design rule check (DRC) to confirm it meets the process' requirements for sizing and spacing. Below you can see the DRC confirmation for the single bit DAC with no errors. This portion was also extracted and LVS confirmation was determined before moving on to the full 10-bit design.
Figure 4: DRC confirmation for single bit DAC portion
Figure 5: LVS confirmation for single bit DAC circuit
The single bit DAC portion will now be used 10 times to create a 10-bit DAC. Using metal 1, connections will be made between each instantiation to build the full 10-bit circuit. The overall design will involve the use of 31 10K resistors. Below we can see the final circuit design in layout format showing LVS confirmation.
Figure 6: Full 10-bit DAC layout view with LVS confirmation
Figure 7: Full 10-bit DAC circuit DRC check complete with no errors
Again we see the circuit below in extracted view of the entire 10-bit DAC using the C5 process.
Figure 8: Full 1-bit DAC extracted view
Backup Confirmation
As with previous labs, all files were backed up during the process of completing this lab.