Digital IC Design - Lab 8 - EE421L

Authors: 

Leonardo Ledesma
Jesus Flores-Arellano

Kanoa Hokoana

Emails: 

ledesl1@unlv.nevada.edu

florej29@unlv.nevada.edu 

hokoana@unlv.nevada.edu

December 5th, 2023

   

Lab Description

This lab will focus on the layout and submission preperation to MOSIS for device fabrication. 

 

Pre-Laboratory Procedure

Tutorial 6 was completed prior to the start of this lab and all content was reviewed in its entirety.

 

Laboratory Objectives

Using a 40 pin pad design, the devices listed below should be added being sure to not allow any two devices to share a vdd connection to prevent shorts to ground that would cause all devices to become inoperable.
Global ground can be shared amound devices located on pin 20.

  

Devices Added to the Chip:
- Buck Switching Power supply from F_23 semester
- 31-stage ring oscillator with buffer circuit to drive a 20pF off-chip load
- 6u/600n NAND and NOR
- 12/6 inverter with minimum length
- 6u/600n PMOS and NMOS with all terminals connected to indivdual pins outside of global grounded NMOS
- 25K N-well resistor and 10K hi-res resistor forming a voltage divider

 
Pin definitions, associated schematic and device locations should be included along with a concise testing procedure to verfiy proper operation of each device

  

Laboratory Procedure

Device list with pin locations shown below:

** NOTE: For many logical operations input Pins 12 & 13 are share among devices **

 

DevicePin#SignalValue
Common GND20inputgnd!
NOR Gate8OutputA NOR B
9Inputvdd
12InputA
13InputB
NAND Gate10OutputA NAND B
11Inputvdd
12InputA
13InputB
XOR Gate19OutputA XOR B
18Inputvdd
12InputA
13InputB
12/6 Inverter6OutputAi
7Inputvdd
12InputA
NMOS(Bodu grounded to substrate)21OutputDrain
22InputGate
23InputSource
PMOS14InputBody
15InputSource
16InputGate
17OutputDrain
31 Stage + Buffer34InputEnable
35OutputOscillator Ouput
36Inputvdd
Voltage Divider24Input/Output25k Input
25Input/Output25/10 Common
26Input/Output10k Input
Buck Switching Power Supply37Output3.125V
38InputVout
39Inputvdd
Unused Pins24, 27-33N/AN/A

Chip9_f23 Pinout Table

  

Chip9_f23 Master Schematic

  

Chip9_f23 Master Layout

     

Zoomed Views With Device Locations


Zoomed Views of Chip9_f23

 

 

Chip9_f23 Testing Procedure 

All of these devices where tested prior in other labs can can be located here:
Buck Switching Power supply

NAND and NOR

12/6 Inverter

PMOS and NMOS

- Voltage Divider


  

At any point in the testing procedure Pin 20 can be disonnected at any moment disabling all functionality of the chip and internal devices. 

This concludes the testing procedure.

 

All design files, schematics, layouts and extracted views can be found here with top level layouts/schematics under MASTER_CHIP

 

 

  

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