EE 421L Digital Integrated Circuit Design Laboratory
Fall 2023, University of Nevada, Las Vegas

 

Student lab reports are found here.    

  

Current grades are located here.

 

Lab Chips

Chip1_f23 – Adam, Batya, Ethan  
Chip2_f23 – Kolby, Baylee, Josue  
Chip3_f23 – Isabella, Dillon, Ronnie  
Chip4_f23 – Cody, Dara, Edgar  
Chip5_f23 – Jalen, Martin, Larri  
Chip6_f23 – Sean, Xavier, Homero   
Chip7_f23 – Anthony P., Kyle, Joshua  
Chip8_f23 – Jonathan, Ben, Matthew
Chip9_f23 – Leonardo, Kanoa, Jesus, Anthony L.  
  

Project (NOT a group effort) – design a non-inverting buffer circuit that presents less than 100 fF input capacitance to

on-chip logic and that can drive up to a 1 pF load with output voltages greater than 7V (an output logic 0 is near ground

and an output logic 1 is greater than 7V). Assume VDD is between 4.5V and 5.5V, a valid input logic 0 is 1V or less, a valid

input logic 1 is 3V or more. Show that your design works with varying load capacitance from 0 to 1 pF. Assume the slowest

transition time allowed is 4 ns.

  

First half of the project (schematics and design discussions) of your design and an html report detailing 

operation (including simulations), is due at the beginning of lab on Nov. 22.  

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu and link to your index.htm page.  

Dr. Baker will go over your design with you (in person), including running simulations, when lab meets on Nov. 22.

Your report should detail the design details (why you selected the topology and sizes you did) as well as simulations.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 29.

Dr. Baker will meet with you on Nov. 29 to go over your layout and, again, put your report in the /proj folder in

your directory at CMOSedu. Ensure that there is a link on your project report webpage to your zipped design directory.  

 

November 29 – Lab8 – Generating a test chip layout for fabrication, due December 6
October 25 (assign lab projects) – Lab7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders, due November 8
October 11 – Lab6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder, due October 25 (2 week lab)  
September 27 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 11 (2 week lab)  
September 20 – Lab4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process, due September 27
September 13 – Lab3 – Layout of a 10–bit DAC, due September 20  
September 6 – Lab2 – Design of a 10–bit digital–to–analog converter (DAC), due September 13
August 30 – Lab1 – Laboratory introduction, generating/posting html lab reports, installing and using Cadence, due September 6
Watch the Lab Safety Training video and review the Lab Rules & Regulations here  
   

Instructor: Dr. Baker, R. Jacob   

Lab Assistant (grader): Abraham Castaneda     
Time: Wednesdays from 11:30 to 2:15 PM  

Course dates: Wednesday, August 30 to Wednesday, December 6

Location: TBE B–350  

Holidays: None

Course content – Laboratory based analysis and design of digital and computer electronic systems.

Credits: 1

Corequisite: EE 421; Prerequisite: EE 320L

 

Grading
30% Quizzes
40% Lab Reports

30% Project
 

Policies 

    

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