Digital Integrated Circuit Design - EE 421L

Taught by Professor: R. Jacob Baker, PhD, PE

Authored by Jesus Flores-Arellano

Student Email: florej29@unlv.nevada.edu

Lab Reports

1. Lab 1 - Laboratory introduction, generating/posting html lab reports, installing and using Cadence
2. Lab 2 - Schematic Design of a 10-bit Digital-to-Analog Converter (DAC)
3. Lab 3 - Layout Design of a 10-bit Digital-to-Analog Converter (DAC)
4. Lab 4 - IV characteristics and layout of NMOS and PMOS devices in ON's C5 process 
5. Lab 5 - Design, layout, and simulation of a CMOS inverter
6. Lab 6 - Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder
7. Lab 7 - Using buses and arrays in the design of word inverters, muxes, and high-speed adders. 
8. Lab 8 - Generating a test chip layout for submission to MOSIS for fabrication

Lab Project

Project - Non-Inverting Buffer

Return to EE421L Fall 2023 Student lab reports