EE 421L
Digital
Integrated Circuit Design Laboratory
AUTHOR:
Bryan Kerstetter
EMAIL:
kerstett@unlv.nevada.edu
FALL
2019
Laboratory
Report Repository
No link? Check the due date!
|
Laboratory
|
Title
|
Date
Due |
|
Laboratory Introduction,
Generating/Posting HTML Lab Reports, Installing and Using Cadence |
09/04/2019 |
|
|
Design of a 10-Bit
Digital-to-Analog Converter (DAC) |
09/11/2019 |
|
|
Layout of a 10-Bit DAC |
09/18/2019 |
|
|
IV Characteristics and
Layout of NMOS and PMOS Devices in ON’s C5 Process |
09/25/2019 |
|
|
Design, Layout, and
Simulation of a CMOS Inverter |
10/09/2019 |
|
|
Design, Layout, and
Simulation of a CMOS NAND Gate, XOR Gate, and Full-Adder |
10/23/2019 |
|
|
Using Buses and Array in
the Design of Word Inverters, Muxes, and High-Speed Adders |
11/06/2019 |
|
|
CMOS x4 Clock Multiplier
[Currently Only Schematic and Simulation; Later Layout] |
11/20/2019 |
|
|
Generating a Test Chip
Layout for Submission to MOSIS for Fabrication |
12/04/2019 |
Return to EE
421L Fall 2019 Page
Return to Dr. Baker’s CMOSedu homepage
