EE 421L
Laboratory
3:
Layout of a 10-Bit Digital-To-Analog Converter (DAC)
AUTHOR:
Bryan Kerstetter
EMAIL:
kerstett@unlv.nevada.edu
SEPTEMBER 18, 2019
General
Overview
This laboratory
is an extension of the previous laboratory. In the previous laboratory, a
voltage-mode 10-bit DAC was designed based upon a given topology. In this
laboratory, the designed DAC will be laid out.
Prelab
As instructed, all the previous work was backed up
from the laboratory and lecture. The first half of tutorial
1 was completed in Laboratory 1. The goal of this prelab is to finish the
second half of tutorial
1. The second half of tutorial 1 focuses primarily on the layout of the
resistive voltage divider seen in Figure 1. A symbol of the circuit as seen in
Figure 1 was created and displayed in Figure 2.
Figure 1
Figure 2
The symbol was then tested (see Figure 3). An input
voltage of 1V was placed at the input. At the output, the output voltage is
0.5V (see Figure 4).
Figure 3
Figure 4
A resistor was made from the n-well as seen in
Figure 5. The resistance of a resistor can be calculated in the following
manner:
[1]
According to the C5 process
from On Semiconductor, the resistance of a square of n-well is 855Ω
(Figure 6). The lambda value, given by MOSIS,
indicates that the smallest size step is 0.3µm (Figure 5). Therefore, any
dimension of the resistor, must be perfectly divisible by 0.3µm. For instance,
let the width be 4.5µm. 4.5/0.3 is 15. Therefore, 4.5µm is a valid width. Now,
according to the laboratory 2 instructions, the resistance value, R, of
the DAC should be 10kΩ. Additionally, the resistance of each resistor in
the resistive voltage divider is 10kΩ. Therefore, we may plug the known
information into the Equation 1 and fin.
[2]
[3]
However, a length of 
would be impossible to implement
in the layout because the smallest voltage increment is
. The length was adjusted until the resistance of the extracted resistor
was around 10k (as seen in Figure 9). Specifically, the resistance is 10.21k Ω.
The final length of the resistor was 56.1µm (as
indicated by a ruler in Figure 10 and the n-well rectangle properties in Figure
11). 56.1µm is a valid dimension because it is divisible by 0.3µm
(56.1/0.3=187). Interestingly, the calculation given in Equation 3 was not
precise. This was most likely since the 
value was incorrect. The correct can be calculated by in the
following manner by using a known resistance with its associated width and
length:
[4]
[5]
Equation 3 can be recalculated to find the true value.
Figure 5: Click image to be directed to the source.
Figure 6: Click image to be directed to the source.
Figure 7
Figure 8
Figure 9
The length and the width of the n-well resistor can be
determined by either looking at the object’s properties {press Q in Cadence}(Figure
10) or by using a ruler {press k in Cadence}(Figure 11-12).
Figure 10
Figure 11
Figure 12
The
voltage divider was fully laid out and passed the DRC (Figure 13) and LVS (Figure
14).
Figure 13
Figure 14
Laboratory Procedure
A 1/3 voltage divider schematic (Figure 15) was
created. This 1/3 voltage divider was then laid out (Figure 16). The layout
passed both the DRC and the LVS (Figure 17).
Figure 15
Figure 16
Figure 17
Once the voltage divider block had been created, the
DAC schematic as seen in Figure 18 was used as a guide to produce the layout of
the DAC (see Figure 19).
Figure 18
Figure 19
The DAC layout as seen in Figure 19 passed both the
DRC and the LVS (see Figure 20). The ten-bit DAC was also tested and proved to
be successful (see Figure 21). Additional DAC simulations can be seen in the previous
laboratory. All the design files for this laboratory were backed up on
Google Drive (see Figure 22).
Figure 20
Figure 21
Figure 22
Return to EE
421L Fall 2019 Page
Return to Dr. Baker’s
CMOSedu homepage
