EE 421L
Digital
Integrated Circuit Design Laboratory
Laboratory
Report 2: Design of a 10-Bit Digital-To-Analog Converter (DAC)
AUTHOR:
Bryan Kerstetter
EMAIL:
kerstett@unlv.nevada.edu
SEPTEMBER
11, 2019
General Overview
A digital-to-analog converter or DAC is a device that converts a digital
signal to an analog signal. In this laboratory DACs will be explored. In
Chapter 30 entitled Implementing Data Converters of Dr. Baker’s book CMOS Circuit Design, Layout and
Simulation, multiple topologies of DACs are discussed. There is a
distinguishing factor in the DACs discussed in Chapter 30. Some DAC topologies
have an Op-Amp while others do not. The advantage of a DAC that features an
Op-Amp is that that the DAC can drive an arbitrary impedance. Whereas, when
there is no Op-Amp in a DAC the impedance that the DAC can drive is limited to
certain factors. According to Dr. Baker’s book, the impedance, “must either be
known, capacitive, or very large” (CMOS 3rd Edition, pg. 1038). In this laboratory, a topology with no op-amp
will be implemented (as seen in Figure 1). There are, however, advantages to
using a DAC without an op-amp. These advantages include faster speeds and
ensured stability.
Figure 1
Prelab
The lab2.zip file
was downloaded, unzipped, and placed into the newly created directory entitled lab2.
Additionally, it was ensured that the appropriate DEFINE statement
was found in the cds.lib file.
Figure 2
The contents of the lab2.zip
were placed in the newly created lab2 directory. Then the cell entitled sim_ideal_ADC_DAC was opened as seen below.
Figure 3
In sim_ideal_ADC_DAC
we have a system that contains both a 10-bit ideal ADC and a 10-bit ideal
DAC. The purpose of this system is to demonstrate the function of both an
analog-to-digital converter (ADC) and a digital-to-analog converter (DAC).
Voltage
Resolution of ADC-DAC System
The voltage resolution
of the system is dependent upon the bit width of the digital signal. Here, in
this system, the bit width is 10. Therefore, the voltage resolution of the
system can be determined by 2 to the power of the bit width. In this case, the
voltage resolution of the system can be described by 2bit width or 210,
which is 1024. Therefore, the ADC can sample 1024 increments of voltage. The voltage
increment is dependent upon the supply voltage to the system.
Additionally,
the voltage increment also represents the least significant bit of the system.
The voltage increment (or 1 LSB) also depicts the minimum ADC input voltage
change to observe a change in the digital output of the ADC. One voltage
increment or LSB can be calculated in the manner seen below:
ADC:
Relation of the Input Voltage to the Digital Signal
The input sinusoid Vin
is the input to the ADC. The ADC samples the analog signal, Vin,
every clock cycle. The analog signal is then converted into a 10-bit digital
signal, B[9:0] by the ADC. B[9:0] is a digital interpretation of the analog
signal. This 10-bit digital signal, B[9:0],
then becomes the input of the DAC. The value of the digital signal can be
calculated as such:
DAC:
Relation of the Digital Signal and the Output Voltage
The DAC then converts
the digital signal into a reconstructed analog signal. The DAC converts the
digital value into an analog voltage value (see formula below) and updates Vout every clock signal. The better the
ADC-DAC system is the more similar the Vout
signal will be to Vin. In order to have a better ADC-DAC system, one
would need to increase both the voltage resolution of the system and temporal
resolution. One may increase the temporal resolution by increasing the clock
frequency.
Figure 4
Figure 5
In Figure 4, the Vin
signal has the following properties:
§ DC Offset: 2.5V
§ Amplitude: 2.5V
In Figure 5, the Vin
signal has the following properties:
§ DC Offset: 2.5V
§ Amplitude: 0.02V
The swing of the
output and input signals, in Figure 5, is rather small. The swing small enough
such that one can easily see the voltage increments of the output signal. There
are 8 increments from a valley to a peak. We also know that the voltage swing
is 40mV. Therefore, from Figure 5 we may approximate the voltage increment in
the following manner:
Description of Laboratory Procedures
Drafting the 10-Bit Voltage-Mode DAC Without
Op-Amp
A simple 10-bit ADC was drafted in Cadence, adhering to the topology
given in Figure 1. An essential component of the voltage-mode DAC without an
op-amp is a simple voltage divider. Like the previous laboratory, we drafted a
voltage divider in Cadence. As instructed, each 2R resistor was
implemented with two separate 10kΩ resistors in series. The symbol was
created based upon the voltage divider circuit given in Figure 7. In Cadence a
symbol can be created when a schematic is open in the following manner: Create
→Cellview→From Cellview.
While also ensuring that the following is the case:
Figure 6
The symbol created
from Figure 7 is depicted in Figure 8. The 5-bit DAC given in Figure 1 was used
to create the 10-bit DAC given in Figure 9. The constructed 10-bit DAC was
created from 10 voltage divider blocks. A symbol of the constructed 10-bit DAC
was created as seen in Figure 10. The symbol depicted in Figure 10 was based
upon the provided symbol entitled Ideal_10-bit_DAC, however it was
customized so that it could obviously be differentiated from the Ideal_10-bit_DAC
provided. Our design did not require VDD,
Figure 7: Voltage Divider Block
Figure 8: Voltage Divider Block Symbol
Figure 9: Voltage-Mode (10-bit) DAC Without
Op-Amp
Figure 10: Voltage-Mode (10-bit) DAC Without Op-Amp Symbol
DAC Output Resistance
Figure 11: Voltage-Mode DAC Without Op-Amp General Topology
The DAC output
resistance can be determined by grounding the digital inputs and adding the
resistors up in parallel and series. According to the process below, one may
say that for any n-bit Voltage-Mode DAC Without Op-Amp, the output resistance
will simply be R. In our case the output resistance will be 10kΩ
(see the Drafting the 10-Bit
Voltage-Mode DAC Without Op-Amp section).
Beginning
from the bottom…
Now
we add to resistors in series and we have an identical case to the first case.
This
process may continue for any n-bits and the output resistance will, in fact, be
R Ohms.
DAC Delay While Driving a Capacitive Load
Theoretically, we know that the time delay of an RC circuit can be said
to be the following:
In Figure 13 we see the definition of time delay. Time delay is the time
at which it takes for the voltage to rise to half the voltage of the pulse. We
see that the We may simplify Figure 11 while considering the addition of a 10pF
capacitive load as seen in Figure 12. Here we see that the voltage-mode DAC can
be simplified to a simple RC circuit. Therefore, the time delay can be
calculated in the following manner:
To test the delay while the DAC is driving a capacitive load, one may
ground all DAC inputs except B9. The input, B9, is then connected to a pulse
source such that the pulse jumps from GND to VDD. A circuit used to test the
DAC delay while driving a capacitive load is seen in Figure 14. In Figure 15,
we see the results of the simulation. In the simulation we see that the time
delay is 69.53ns. The theoretical and simulation results are compared in Table
1.
Table 1
|
Theoretical |
Simulation |
|
70ns |
69.53ns |
Figure 12
Figure 13
Figure 14
Figure 15
DAC Under
No Load
For all simulation results,
the system seen in Figure 3 is used. The given ideal DAC is replaced with the
DAC that I created. The circuit used to test the operation of the DAC is
depicted in Figure 17. Here we see with
no load conditions; the DAC works properly (see Figure 18). Initially, the
simulation would not converge and would cease at 350ns. The convergence was
forced by the following procedure:
While in ADE, navigate
to Simulation ® Options ® Analog and ensure that the following is the case…
Figure 16
Figure 17
Figure 18
DAC Under
Resistive Load
A 10kW resistor was added to the output of our DAC
(see Figure 19). The simulation results are seen in Figure 20. The smaller the
resister the smaller the output swing. Likewise, a larger resistor results in a
larger output swing. Here, when the resistive load is 10kW , the output swing is from 0V to 2.5V. The
voltage increments are still visible as steps. Also, the output sinusoid, no
longer swings about 2.5V, but rather 1.25V.
Figure 19
Figure 20
DAC Under
Capacitive Load
The resistor was
replaced with a 10pF capacitive load (see Figure 21). The simulation result of
the DAC under a capacitive load is seen in Figure 22. Adding a capacitor to the
output of a DAC smooths the output of the DAC such that the output appears to
be a continuous voltage trace. However, the downside of adding a capacitive
load is that the voltage swing is severely reduced. The voltage swings from 1V
to 3V. Interestingly, unlike the case of a resistive load, the sinusoid swings
about 2.5V. Additionally, by adding a capacitor, lag is introduced to the
system. Therefore, the output signal lags the input signal.
Figure 21
Figure 22
DAC Under
a Resistive and Capacitive Load
Finally, we add both
capacitor and a resistor to the output of the DAC. The result is a combination
of the effects of adding a resistive and a capacitive load individually. The
voltage swings from 0.2V to 2.3V. Therefore, the output trace swings about 1.25V.
Likewise to the previous example the output signal lags the input signal (due
to the 10pF capacitive load).
Figure 23
Figure 24
Switch
Resistance
In this situation, the
digital signals are provided by MOSFETs in the ADC. If the MOSFETs equate to a
resistance that is not small compared to R. The structure of the voltage-mode
DAC will change and result in a change of the output resistance and effect the
performance of the DAC. A circuit was created to observe how the DAC would
operate when there is a 30kW resistor that separates the output of the ADC and the input of the
DAC (see Figure 25). As seen in Figure 6, the DAC operates poorly. The voltage
increments are far more unpredictable. It is far more difficult for the DAC to
recreate the original analog signal. This extra added impedance can also effect
the output resistance and effect load driving capabilities.
Figure 25
Figure 26
Design
File Back Up
The cadence design files
for this laboratory were downloaded and backed up on Google Drive.
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421L Fall 2019 Page
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