EE 421L
Digital Integrated Circuit Design Laboratory
Laboratory Report 6: Using Buses and Arrays in the Design of Word Inverters, Muxes, and High-Speed Adders

AUTHOR: Bryan Kerstetter

EMAIL: kerstett@unlv.nevada.edu

NOVEMBER 6, 2019

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General Overview

This laboratory will introduce buses and arrays in Cadence. These buses and arrays will be used to design word inverters, logic gates, muxes, demuxes, and high-speed adders.

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Prelab

The prelab for this laboratory involves going through Tutorial 5 on CMOSedu. This tutorial regards the design, layout, and simulation of a ring oscillator. A ring oscillator consists of an odd number of inverters connected in series (see Figure 1).

Figure 1

A simple schematic was created to represent a 31-stage ring oscillator. Arrays and buses were used to simplify the schematic of the ring oscillator. If arrays and buses were not used, there would literally be 31 inverters visible in the schematic.

Figure 2

The simulation results of the ring oscillator are seen below. An initial condition was made to kickstart the ring oscillator. The initial condition was to set osc_out to 0. Regarding simulation, if an initial condition is not specified (0 or VDD) then the ring oscillator may not function properly. In which case, osc_out will not oscillate, but be stagnate at the value of 2.5V, the switching point of the inverter. In real life circuitry, noise kickstarts and prevents the stagnation observed in simulation.

Figure 3

Layout of ring oscillator.

Figure 4

Layout passes DRC and LVS.

Figure 5

A symbol is created to represent our ring oscillator. The schematic seen above is what is used to create the ring oscillator symbol (minus the power supply circuitry).

Figure 6

The symbol was then used to create the following circuit that will be used to simulate the extracted form of the layout. When one simulates an extracted simulation, the netlist is based upon the layout, not the schematic.

Figure 7

Figure 8

Figure 9

Extracted simulation confirmed.

Figure 10

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Laboratory Procedure

I. Design and Simulation of a 4-bit Inverter

4-Bit Inverter

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

II. Design and Simulation of 2 8-bit Word Logic Gates

a. Construction of 2 Input Logic Gates

i. NAND Gate

Figure 16

Figure 17

ii. NOR Gate

Figure 18

Figure 19

iii. Inverter

Figure 20

Figure 21

iv. AND Gate

Figure 22

Figure 23

v. OR Gate

Figure 24

Figure 25

b. Construction of 8-Bit Word Logic Gates

i. 8-bit NAND

Figure 26

Figure 27

ii. 8-bit NOR

Figure 28

Figure 29

iii. 8-bit Inverter

Figure 30

Figure 31

iv. 8-bit AND

Figure 32

Figure 33

v. 8-bit OR

Figure 34

Figure 35

c. Simulation of all 8-Bit Gates

Figure 36

Figure 37

Correct results are observed for all logic gates.

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III. Multiplexors and De-multiplexors

a. Design and Simulation of 2:1 MUX

Figure 38

Figure 39

Figure 40

Figure 41

b. Design and Simulation of 2:1 MUX/DEMUX

Figure 42

Figure 43

Figure 44

c. Design and Simulation of 2:1 MUX with a Single Select Input

Figure 45

Figure 46

Figure 47

d. Design and Simulation of an 8-bit 2:1 MUX

Figure 48

Figure 49

Figure 50

Figure 51

IV. Design, Simulation, and Layout of an AOI Implementation of a 8-bit Full Adder

a. A Single AOI Full Adder

Figure 52: Fig. 12.20 in CMOS book

Figure 53

Figure 54

Figure 55

Figure 56

Table 1

A	B	Cin	S	Out	Confirmation in Waveform
0	0	0	0	0	Confirmed
0	0	1	1	0	Confirmed
0	1	0	1	0	Confirmed
0	1	1	0	1	Confirmed
1	0	0	1	0	Confirmed
1	0	1	0	1	Confirmed
1	1	0	0	1	Confirmed
1	1	1	1	1	Confiremd

b. Layout of AOI Full Adder

Figure 57

Figure 58

Passes DRC and LVS

Figure 59

d. Circuit Design of 8-Bit AOI Full Adder

Figure 60

Figure 61

e. 8-Bit AOI Full Adder Simulation

Test 1

Figure 62

Figure 63

Table 2

	Cout	S<7>	S<6>	S<5>	S<4>	S<3>	S<2>	S<1>	S<0>
A		1	1	1	1	1	1	1	1
B		0	0	0	0	0	0	0	0
	0	0	0	0	0	0	0	0	0

Test 2

Figure 64

Figure 65

Table 3

	Cout	S<7>	S<6>	S<5>	S<4>	S<3>	S<2>	S<1>	S<0>
A		0	1	0	1	0	0	0	1
B		0	1	0	1	1	1	1	0
	0	1	0	1	0	1	1	1	1

f. Layout of 8-Bit AOI Full Adder

Figure 66

Figure 67

Figure 68

Figure 69

Figure 70

Passes DRC and LVS

Figure 71

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