EE 421L
Digital Integrated Circuit Design Laboratory
Project: CMOS 4x Clock Multiplier

NOVEMBER 13, 2019

General Overview

Clock Multiplier Introduction

A clock multiplier has an input clock with frequency , such that the output of the clock multiplier is a clock with frequency (see Figure 1). Where is the multiplier of the clock multiplier. Or in other words the output clock will have cycles for every input clock cycle. A simple clock multiplier can be implemented with a XOR ( gate and a delay element (see Figure 2). The delay element delays the input clock signal. The input clock signal and the delayed input clock signal is then processed by the XOR gate (see Figure 3). The result is an output clock with a clock frequency multiplied by a factor of two. Generally, for digital clocks have a 50% duty cycle. Therefore, it is preferred to have an output clock with a 50% duty cycle. For the output clock to have 50% duty cycle the input clock must be delayed by precisely or . Where is the period of input clock frequency. To further multiply the clock signal, one may cascade the clock multiplier elements seen in Figure 2. Two clock multiplier elements cascaded together, results in clock multiplier with (see Figure 4). In the case of the clock multiplier in Figure 4. The first delay must be seconds long and the second delay must be seconds long to ensure that the output clock has a 50% duty cycle.

Figure 1

Figure 2

Figure 3

Figure 4

Project Specifications

This project regards the design, simulation, and layout of a 4x clock multiplier. It is assumed that the 4x clock multiplier has an input frequency of 9-11MHz. The designed clock multiplier should then generate a clock with a frequency of 36-44MHz. It is assumed that the input of clock has a 50% duty cycle.

Clock Multiplier Design

Background

The input frequency of the clock multiplier is said to be 9-11Mhz. Therefore, the clock may be 9, 10, or 11MHz. The delays required for each respective frequency can be calculated as follows:

[1]

[2]

[3]

9MHz

10MHz

11MHz

One might assume that you could implement the delays associated with 10MHz. After all, 10MHz is in the middle of the input frequency range. However, the period of the output clock frequency will be 23-28ns. And if the input frequency is not 10MHz. the output duty cycle will not precisely be 11MHz. This is due to the fixed delay elements causing the output clock periods to be 4ns off. Therefore, ideally, a clock multiplier could be designed such that you could select delays of the delay elements. The delays associated with 9MHz could be selected when the input clock frequency is 9MHz. Likewise, the delays associated with 10MHZ could be selected when the input clock frequency is 9MHz. The same could be said for 11Mhz. Therefore, ideally the delay elements could produce delays that are a function of frequency, such that Equations 1-3 are fulfilled.

Creating a Voltage Controlled Delay

A current starved inverter can be used to create voltage-controlled oscillator (see Figure 19.14 in Dr. Baker’s CMOS book). The voltage-controlled oscillator depicted in Figure 19.14, can be converted into a voltage-controlled delay by removing the feedback (the connection between the output of the last invert and the input of the first inverter). MOSFETs M2 and M3 behave as inverter, but M1 and M4 act as current sources, limiting the current supplied to the inverter. The current supplied to the inverters are determined by the biasing circuit formed by M5 and M6. The current through the NMOS is proportional to V_GS. Therefore, the greatest current results in the shortest delay. The greatest current is when VDD is equal to VDD, so the shortest delay is when the voltage control is VDD. The smaller the current, the greater the delay. Therefore, it can be said:

The Clock Multiplier

A clock multiplier was designed in the topology given in Figure 4. Voltage-controlled delay elements were implemented into the clock multiplier. Implementing the voltage-controlled delay elements into the clock multiplier allows for one to ensure that the output clock has a 50% duty cycle. Voltage control values for 9MHz, 10MHz and 11MHz were found and then voltage dividers were created to produce the specific voltage controls. The minimum delay allows for the input of a 11MHz clock signal, allowing the delays to be adjusted to adequately multiply a signal with a slower frequency (i.e. 10 or 9MHz). A 4:1 multiplexor was then created to select what voltage level will be fed to the voltage-controlled delays. Table 1 demonstrates the three voltage codes that were implemented. Any combination, on the table will produce an output signal that is multiplied by four with a 50% duty cycle. Additionally, if the voltage supply, VDD, is changed to 4, 4.5, 5, 5.5, or 6V, a voltage control code can be selected to ensure that input 9-11MHz signal is multiplied by four with a 50% duty cycle on the output signal. Additionally, if a voltage code of 00 is selected, an arbitrary voltage, Ain, can be selected to control the voltage-controlled delay elements. Therefore, the user of the designed clock multiplier can specify Ain to ensure that the output clock signal is optimized.

The Clock Multiplier Consists of the Following 7 Modules

1. The Buffer

2. The First Voltage-Controlled Delay: Delay Long

3. The First Voltage-Controlled Delay: Delay Short

4. The Current Starved Inverter

5. The Exclusive Or () Gate

6. The Inverter

7. The 4:1 Multiplexor

Table 1

			VDD=
S1	S2	Voltage Control	4	4.5	5	5.5	6
0	0	Ain	Ain	Ain	Ain	Ain	Ain
0	1	V1	7MHz	8MHz	9MHz	10MHz	11MHz
1	0	V2	8MHz	9MHz	10MHz	11MHz	12MHz
1	1	VDD	9MHz	10MHz	11MHz	12MHz	13MHz

Table 2

	VDD=
Voltage Control	4	4.5	5	5.5	6
Ain	Ain	Ain	Ain	Ain	Ain
V1	2.20	2.48	2.75	3.03	3.30
V2	2.58	2.91	3.23	3.55	3.88
VDD	4V	4.5V	5V	5.5V	6V

Figure 5: 4x Clock Multiplier Symbol with a Portion of Table1

Figure 6: 4x Clock Multiplier Circuitry

1. The Buffer

The buffer module is used throughout the design of the clock multiplier. The buffer ensures that the rising and falling edges are quick.

Figure 7: Buffer Symbol

Figure 8: Buffer Circuit

2. The First Voltage-Controlled Delay: Delay Long

According, to Equations 1-3, this first voltage-controlled delay must be able to produce a delay range of 22-28ns, to ensure that the output signal has a 50% duty cycle (when the input of the clock multiplier is 9-11MHz). The delay of this module is dependent upon the voltage at node Vin. This delay element has a biasing circuit to bias the current-starved inverters. Additionally, a calibration inverter is included to calibrate the delay. Then finally a buffer, with an adjusted switching point is implemented to ensure that the output signal has a 50% duty cycle. Finally, a buffer module is placed to ensure that the rising and falling edges are still fast after the delay elements.

Figure 9: Delay Long Symbol

Figure 10: Delay Long Circuit (22-28ns)

3. The First Voltage-Controlled Delay: Delay Short

According, to Equations 1-3, this first voltage-controlled delay must be able to produce a delay range of 11-14ns, to ensure that the output signal has a 50% duty cycle (when the input of the clock multiplier is 9-11MHz). The delay of this module is dependent upon the voltage at node Vin. The delay of Delay Short will be half the time of the delay of Delay Long. This delay element has a biasing circuit to bias the current-starved inverters. Additionally, a calibration inverter is included to calibrate the delay. Then finally a buffer, with an adjusted switching point is implemented to ensure that the output signal has a 50% duty cycle. Finally, a buffer module is placed to ensure that the rising and falling edges are still fast after the delay elements.

Figure 11:Voltage-Controlled Delay Short Symbol

Figure 12: Delay Long Circuit (9-11ns)

4. The Current Starved Inverter

A current starved inverter module is designed in accordance to what is depicted in Figure 19.14 of Dr. Baker’s CMOS book. The symbol allows one to specify Vbiasp and Vbiasn.

Figure 13: The Current-Starved Inverter Symbol

Figure 14: Current-Starved Inverter Schematic

5. The Exclusive Or () Gate

Figure 15: The Exclusive Or Symbol

Figure 16: Exclusive Or Circuit

6. The Inverter

Figure 17: The Inverter Symbol

Figure 18: Inverter Schematic

7. The 4:1 Multiplexor

Figure 19: 4:1 Multiplexor Symbol

Figure 20: 2:1 Multiplexor/Demultiplexer Implemented with CMOS Pass-Gates

Figure 21

Figure 22:

Figure 23

Figure 24: 4:1 MUX

Future Design Improvements

Obviously, one downside of the clock multiplier design. Is having to specify the correct voltage control code to ensure that the output has a 50% duty cycle. It may be possible to add to the clock multiplier system such that a feedback loop is implemented (possibly in a manner seen in Figure 25). When the output duty cycle is 50%, the average output voltage is VDD/2. Therefore, a voltage divider can be created to produce a reference VDD/2. The average output voltage can then be compared to the reference VDD/2 voltage. A voltage comparator can then be implemented such that the output voltage of the comparator adheres to the following table:

Table 3

Comparator Output Voltage	Meaning
VDD	> 50% Duty Cycle of Output Signal
GND	< 50% Duty Cycle of Output Signal

Then based upon the output of the voltage comparator. Voltage Control Generation circuitry can be designed. This circuitry can then either produce a linear increasing or linear decreasing voltage signal. This voltage signal could then be fed to the Ain port of the clock multiplier. The Voltage Control Generation circuitry could either consist of either a simple RC circuit, Integrator, or other circuitry. It is possible, that even further modification to the existing clock multiplier would be required. The end result would be a clock multiplier system that automatically ensures that the output clock frequency has a 50% duty cycle. Therefore, this system would be resistant to variances in temperature, supply voltage, and input frequency.

Figure 25

The idea of using a feedback control loop for clock multipliers is not foreign. For instance, the NB3N511, a commercial clock multiplier by ON Semiconductor features feedback control by implementing Phase-Locked-Loop (PLL) design techniques. The logic diagram of the NB3N511 can be seen in Figure 26. The datasheet of the NB3N511 asserts that the output duty cycle will be between 45%-55%.

Figure 26

Clock Multiplier Simulation

Simulation Platform

A schematic was drafted to simplify the testing and simulation of the designed clock multiplier (see Figure 28). Variables were used to specify, VDD, S1, and S2 (see Figure 27). The frequency can be specified by labeling a positive terminal of a pulsed voltage source in.

Figure 27

Figure 28

Table 1 will be used throughout the simulation process. All values within the table have been confirmed to produce an output clock with a 50% duty cycle.

			VDD=
S1	S2	Voltage Control	4	4.5	5	5.5	6
0	0	Ain	Ain	Ain	Ain	Ain	Ain
0	1	V1	7MHz	8MHz	9MHz	10MHz	11MHz
1	0	V2	8MHz	9MHz	10MHz	11MHz	12MHz
1	1	VDD	9MHz	10MHz	11MHz	12MHz	13MHz

Figure 29: Table 1

Simulations Negating Control (Fixing Control Code to 10)

To help visualize duty cycle and period consistency, two equ-size gold boxes will be placed on two adjacent troughs.

The goal of the implementation of voltage-controlled delay elements in our clock multiplier design was to ensure that the output clock had a 50% duty cycle despite voltage supply and frequency variances. In order to demonstrate why, the implementation of voltage-control delays was so important, we will use the designed clock multiplier as if voltage-controlled delays were not implemented. Therefore, we will fix the control code of 10 with a supply voltage of 5V for all simulations in this section. The control code of 10 is optimized for an input of 10MHz with a voltage supply of 5V.

10 MHz; Select Code = 10; VDD = 5V

Figure 30

Great, the clock multiplier outputs a perfect 50% duty cycle with an input frequency of 10MHz. What happens when the input frequency is 9MHz, while still keeping the control code fixed?

9MHz; Select Code = 10; VDD = 5V

Figure 31

The output duty cycle is no longer 50%, nor are the periods consistent. In the next simulation section, it will be shown that the 50% duty cycle and period consistency can be restored by changing the control code to 01. Now, what happens when the input frequency is 11MHz, while still keeping the control code fixed?

11 MHz; Select Code = 10; VDD = 5V

Figure 32

Again, we see that, the output duty cycle is no longer 50%, nor are the periods consistent. In the next simulation section, it will be shown that the 50% duty cycle and period consistency can be restored by changing the control code to 11.

Now, we will fix both the input frequency and select code for all subsequent simulations in this section. The input frequency will be fixed at 10MHz and the select code, will again be fixed at 10. However, VDD will be varied.

10 MHz; Select Code = 10; VDD = 4.5V

Figure 33

Here, we see that the decrease in supply voltage resulted in the destruction of period consistency and eliminated the 50% duty cycle. In the next simulation section, it will be shown that the 50% duty cycle and period consistency can be restored by changing the control code to 11. What happens if we change VDD to 5.5V?

10 MHz; Select Code = 10; VDD = 5.5V

Figure 34

Simulations Allowing Control

The simulation of all conditions as seen in Table 1 is seen in Table 4. For all simulations, the teal trace the input and the red trace is the output. Table 4 demonstrates that the control code ({S1,S2}) allows for one to be able to optimize the clock multiplier explicitly. However, if a feedback control system was implemented, as described in the section Future Design Improvements, the clock multiplier would automatically be optimized. It can be seen that the issues of duty cycle and period inconsistency witnessed in the previous section, Simulations Negating Control, are fixed in this section.

Note: To view larger image right click on the image and select ‘view image in new tab.’

Table 4

{S1,S2}

4.5V

5.5V

Input Frequnecy = 7MHZ

Input Frequnecy = 8MHZ

Input Frequnecy = 9MHZ

Input Frequnecy = 10MHZ

Input Frequnecy = 11MHZ

Input Frequnecy = 8MHZ

Input Frequnecy = 9MHZ

Input Frequnecy = 10MHZ

Input Frequnecy = 11MHZ

Input Frequnecy = 12MHZ

Input Frequnecy = 9MHZ

Input Frequnecy = 10MHZ

Input Frequnecy = 11MHZ

Input Frequnecy = 12MHZ

Input Frequnecy = 13MHZ

Temperature Simulations

The voltage supply, input frequency, and control code will be fixed for the simulations in this section. The voltage supply will be fixed to 5V. Second, the input frequency will be set to 10MHz. Finally, the control code will be set to 10. All previous simulations were conducted at room temperature (27º C). However, the purpose of this section is to see how the clock multiplier responds to temperature. Therefore, we will first set temperature to a variable by the name of temp (as seen in Figure 35). Parametric analysis will then be performed to simulate the clock multiplier at the temperatures of 0º, 20º, 40º, 60º, 80º, and 100º C (as seen in Figure 36).

Figure 35: As seen in ADE L

Figure 36: Parametric Analysis

10 MHz; Select Code = 10; VDD = 5V

The First Pulse

Figure 37: 0º, 20º, 40º, 60º, 80º, and 100º C

As seen in Figure 37, we find the following proportionality to be true regarding the first pulse:

10 MHz; Select Code = 10; VDD = 5V

A Couple Cycles

Figure 38: 0º, 20º, 40º, 60º, 80º, and 100º C

Any variances in the output waveform, could be corrected by adjusting the voltage-controlled delay elements. Perhaps the control codes 01, 10, and 11 could optimize the output waveform at certain temperatures. Ideally, the feedback control system, described in the section Future Design Improvements, could be implemented to automatically optimize the clock multiplier. The feedback system would result in the output having a 50% duty cycle despite variances in temperature.

Clock Multiplier Layout

Layout Overview

The clock multiplier layout can be described by the following sequence of images. The cell frame size was 27µm (measured from the bottom of the ntap metal1 to the top of the ptap metal1). The layout was then wrapped around to save space. Layout size was used in order to maximize performance in the design (i.e. the addition of voltage-controlled delays, resistive voltage dividers, 4:1 multiplexor, and long width buffers). The final layout has an area of .

Figure 39

Figure 40

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

A Note Regarding Resistive Voltage Dividers Featured in the Final Layout

Figure 50: Click the above graphic to go to the IC Resistor Geometry Calculator

Since there was no power consumption requirement, smaller resistance values were implemented to minimize layout area. As you may recall, our original schematic as seen in Figure 6 called for three resistance values. The three resistance the original schematic called for were 818Ω, 1kΩ, and 1.857kΩ. These resistance sizes are rather small and would result in tiny hires poly resistors. A factor to consider when using smaller resistors is the effect of the end connection resistance upon the total effective resistance of the resistor. Larger resistances minimize the effect of the end connection resistance upon the final effective resistance. Therefore, to improve resistive matching and to minimize the effect of end connections, four resistors were used in parallel. Therefore, the schematic corresponding to the final layout is seen in Figure 51.

My IC Resistor Geometry Calculator was used for resistor calculations. This calculator was created using HTML and JavaScript. Information regarding calculator usage can be found here. Screenshots of calculator use are included in Figure 52, 54 and 56.

Figure 51

Figure 52

Figure 53

Figure 54

Figure 55

Figure 56

Figure 57

DRC and LVS Confirmation

It was ensured that the FET Parameters were examined in the Layout Vs Schematic. This can be done by going to the Virtuoso toolbar and selecting NCSU. Then ensure that the Compare FET Parameters is selected (see Figure 58). The layout passed both DRC and LVS (see Figures 59 and 60).

Figure 58

Figure 59

Figure 60

Confirm Proper Function

The netlist of the layout can be used in simulation to ensure the proper function of the layout. While in ADE L, go to Setup →Environment and type extracted as seen in Figure 61. The simulation platform as seen in Figure 28 is used again to run one final simulation as seen in Figure 62. Other parameters were adjusted (as described in Table 2 and 4) and proper function was confirmed.

Figure 61

10 MHz; Select Code = 10; VDD = 5V

Figure 62

Conclusion

In conclusion, an effective CMOS 4x Clock Multiplier was designed, simulated and laid out successfully while meeting all design specifications. Current-starved inverters were used to create voltage-controlled delay elements. These voltage-controlled delay-elements were implemented alongside 5 other modules to form the final design. To optimize clock multiplier performance, voltage control codes may be used. A summary of these codes and their respective optimization effect is conveyed in Figure 63. In the future, the Ain input of the Clock Multiplier may be used to create a feedback control loop that allows for the system to better withstand voltage supply, temperature, and frequency variance (see Figure 64).

The Clock Multiplier Consists of the Following 7 Modules

1. The Buffer

2. The First Voltage-Controlled Delay: Delay Long

3. The First Voltage-Controlled Delay: Delay Short

4. The Current Starved Inverter

5. The Exclusive Or () Gate

6. The Inverter

7. The 4:1 Multiplexor

			VDD=
S1	S2	Voltage Control	4	4.5	5	5.5	6
0	0	Ain	Ain	Ain	Ain	Ain	Ain
0	1	V1	7MHz	8MHz	9MHz	10MHz	11MHz
1	0	V2	8MHz	9MHz	10MHz	11MHz	12MHz
1	1	VDD	9MHz	10MHz	11MHz	12MHz	13MHz

Figure 63

Figure 64

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