EE 421L Digital Integrated Circuit Design Laboratory
Fall 2019, University
of Nevada, Las
Vegas
Student lab reports are found here.
Current grades are located here.
Lab Chips
Project (not a group effort, each student will turn in their own project) – design a circuit that takes a 9-11 MHz clock signal and generates
a 36-44 MHz clock signal. In other words, design x4 clock multiplier. The input clock is multiplied by 4 and output. Assume the input clock
signal has a 50% duty cycle.
First half of the project (schematics and design discussions) of your design and an html report detailing
operation (including simulations), is due at the beginning of lab on Nov. 13.
Your design report in html should show various input clock frequencies and VDD voltages to show it works.
Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu and link to your index.htm page.
Dr. Baker will go over your design with you (in person), including running simulations, when lab meets on Nov. 13.
Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 20.
Dr. Baker will meet with you on Nov. 20 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.
Ensure that there is a link on your project report webpage to your zipped design directory.
November 27 – Lab8 – Generating a test chip layout for submission to MOSIS for fabrication, due December 4
Instructor: R. Jacob Baker (see office hours at this link)
Lab Assistant: Mario Valles
Time: Wednesday from 11:30 to 2:15 PM
Course
dates: Wednesday, August 28 to Wednesday, December 4
Location: TBE B–350
Holidays: none
Course content – Laboratory
based analysis and design of digital and computer electronic systems.
Credits: 1
Corequisite: EE 421;
Prerequisite: EE 320L
Grading
30% Quizzes
40% Lab Reports
30% Project
Policies
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