EE 421L Digital Integrated Circuit Design Laboratory
Fall 2019, University of Nevada, Las Vegas

 

Student lab reports are found here.    

  

Current grades are located here.

   

Lab Chips

Chip1_f19 – David, Bryan, and Mohammed
Chip2_f19 – Cody, Moriah, and Lizz
Chip3_f19 – Geovanni and Yared  
Chip4_f19 – Shaq, Chris, and Darryl
Chip5_f19 – Steve, Adrian, and John 
Chip6_f19 – Kaylee, Jose, and Peter
  

Project (not a group effort, each student will turn in their own project) – design a circuit that takes a 9-11 MHz clock signal and generates

a 36-44 MHz clock signal. In other words, design x4 clock multiplier. The input clock is multiplied by 4 and output. Assume the input clock 

signal has a 50% duty cycle. 

First half of the project (schematics and design discussions) of your design and an html report detailing 

operation (including simulations), is due at the beginning of lab on Nov. 13.  

Your design report in html should show various input clock frequencies and VDD voltages to show it works.

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu and link to your index.htm page.  

Dr. Baker will go over your design with you (in person), including running simulations, when lab meets on Nov. 13.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 20.

Dr. Baker will meet with you on Nov. 20 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.  

Ensure that there is a link on your project report webpage to your zipped design directory.  

 

November 27 – Lab8 – Generating a test chip layout for submission to MOSIS for fabrication, due December 4
October 23 – Lab7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders, due November 6
October 9 – Lab6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder, due October 23  
September 25 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 9    
September 18 – Lab4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process, due September 25 
September 11 – Lab3 – Layout of a 10–bit DAC, due September 18  
September 4 – Lab2 – Design of a 10–bit digital–to–analog converter (DAC), due September 11  
August 28 – Lab1 – Laboratory introduction, generating/posting html lab reports, installing and using Cadence, due September 4  
Watch the Lab Safety Training video and review the Lab Rules & Regulations here  
   

Instructor: R. Jacob Baker (see office hours at this link)

Lab Assistant: Mario Valles     
Time: Wednesday from 11:30 to 2:15 PM

Course dates: Wednesday, August 28 to Wednesday, December 4

Location: TBE B–350

Holidays: none

Course contentLaboratory based analysis and design of digital and computer electronic systems.

Credits: 1

Corequisite: EE 421; Prerequisite: EE 320L

 

Grading
30% Quizzes
40% Lab Reports

30% Project
 

Policies 

  • Unlike the lectures, laptops can be used during the lab. Please bring your laptop with you to lab!
  • No late work accepted. Regularly being tardy for labs, leaving in the middle of labs, or leaving early is unacceptable without consent of the instructor.
  • Cheating or plagiarism will result in an automatic F grade in the lab
  • Questions for the instructor (only) should be asked in person (not via email). Please talk to the instructor. Please don't email the instructor.
  

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