EE 421L
Digital
Integrated Circuit Design Laboratory
Laboratory
Report 5: Design, Layout, and Simulation of a CMOS Inverter
AUTHOR:
Bryan Kerstetter
EMAIL:
kerstett@unlv.nevada.edu
OCTOBER
8, 2019
General
Overview
This laboratory regards the
design, layout, and simulation of multiple CMOS inverters.
Prelab
All work for this laboratory
and course has been backed up to this point.
Tutorial
3 on CMOSedu regarding cadence was followed. The schematic for a MOSFET
Inverter can be seen in Figure 1.
Figure 1
A symbol was created to represent the schematic.
Figure 2
A layout representing the schematic was produced (see
Figure 3). The extracted view of the layout can be seen in Figure 4.
Figure 3
Figure 4
The layout passed both the DRC and LVS.
Figure 5
A schematic was created to test inverter. A vdd symbol was added to the schematic. A stimulus was set to ensure that vdd was 5V at the start. The input voltage was seeped from 0 to
Figure 6
The resulting plot shows the result of the simulation with the schematic netlist.
Figure 7
The resulting plot shows the result of the simulation
with the extracted netlist.
Figure 8
The
extracted simulation was confirmed to be a simulation of the extracted netlist.
Figure 9
Laboratory
Procedure
What was learned from
tutorial 3 was implemented in the design of two inverters:
·
12u/6u Inverter
[Multiplier = 1]
o PMOS Geometry
§ Width 12µm
§ Length = 600nm
o NMOS Geometry
§ Width = 6µm
§ Length = 600nm
·
48u/24u Inverter
[Multiplier = 4]
o PMOS Geometry
§ Width = 48µm
§ Length = 600nm
o NMOS Geometry
§ Width = 24µm
§ Length = 600nm
1.
12u/6u
Inverter Schematic and Layout
The schematic for the 12u/6u
schematic can be seen below.
Figure 10
Symbol
Figure 11
Layout
Figure 12
Extracted View
Figure 13
Layout Passes DRC and LVS
Figure 14
2.
48u/24u
Inverter Schematic and Layout
The schematic of the 48u/24u
schematic is seen below.
Figure 15
Symbol
Figure 16
Layout
Figure 17
Extracted View
Figure 18
Layout Passes DRC and LVS
Figure 19
3.
12u/6u
Inverter Simulations
The following circuit was
designed to test the 12u/6u inverter’s ability to drive capacitive loads
(Figure 20). A variable was used to represent the capacitance of the capacitor.
Parametric analysis was used to test the inverter driving 100fF, 1pF, 10pF and
100pF capacitive loads (Figure 21). Simulations were conducted both by SPECTRE
and UltraSim. UltraSim can
simulate larger circuits faster, at the cost of accuracy. This decrement in
accuracy can be seen in our UltraSim simulations.
Figure 20
Figure 21
Figure 22
Figure 23
4.
48u/24u
Inverter Simulations
The 48u/24u Inverter was
simulated in a manner similar to the 12u/6u inverter.
Figure 24
Figure 25
Figure 26
It became apparent that the
48u/24u inverter is better at driving capacitive loads than the 12u/6u inverter
(compare Figures 22, 23, 25, and 26). The design files were backed up on Google
Drive (Figure 27). Feel free to look at this laboratory’s design files.
Figure 27
Return to EE
421L Fall 2019 Page
Return to Dr. Baker’s
CMOSedu homepage
