ECE 421L - Digital Electronics Lab
Navigation:
| Lab 01 | Laboratory introduction, generating/posting html lab reports, installing and using Cadence. | Due September 5 |
| Lab 02 | Design of a 10–bit digital–to–analog converter (DAC). | Due September 12 |
| Lab 03 | Layout of a 10–bit DAC. | Due September 19 |
| Lab 04 | IV characteristics and layout of NMOS and PMOS devices in ON's C5 process. | Due September 26 |
| Lab 05 | Design, layout, and simulation of a CMOS inverter. | Due October 10 |
| Lab 06 | Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder. | Due October 24 |
| Lab 07 | Using buses and arrays in the design of word inverters, muxes, and high–speed adders. | Due November 7 |
| Lab 08 | Generating a test chip layout for submission to MOSIS for fabrication. | Due December 6 |
| Project | Design a serial-to-parallel converter. | Due November 14 (Part 1), Due November 21 (Part 2) |
Return to the EE421L
Fall 2018 webpage