Lab 08 - EE 421L 

Authored by Rocky Yasuaki Gonzalez, Michael Loreto, Ethan Tash,

E-mail: gonzar14@unlv.nevada.edu, loreto@unlv.nevada.edu, tash@unlv.nevada.edu

12/5/18

Lab 08: Generating a test chip layout for submission to MOSIS for fabrication.

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Guidelines:

• One, or more if possible, course projects
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is needed for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)   
• Whatever else you would like to fabricate to use the remaining pins on the chip

Images can be clicked increase the size.

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PMOS 6u/0.6u:

G (Gate) -> Pin<37>

D (Drain) -> Pin<38>

S (Source) -> Pin<39>

B (Body) -> Pin<40>

NMOS 6u/0.6u:

G (Gate) -> Pin<14>

S (Source) -> Pin<15>

D (Drain) -> Pin<16>

Inverter 12u/6u:

A (Input) -> Pin<11>

Ai (Output) -> Pin<12>

Vdd_in -> Pin<13>

Voltage Divider (25k and 10k):

Vdiv_in -> Pin<21>

Vdiv_out -> Pin<22>

NAND Gate 6u/6u:

A -> Pin<3>

B -> Pin<4>

AnandB -> Pin<5>

Vdd_nand -> Pin<6>

NOR Gate 6u/6u:

A -> Pin<7>

B -> Pin<8>

AnandB -> Pin<9>

Vdd_nand -> Pin<10>

31-Stage Ring Oscillator w/ Buffer:

pin_out -> Pin<1>

Boost Converter:

Vout -> Pin<28>

Chip3 Design:

Summary of Chip Design:

The Chip layout and Design can be downloaded through this link.

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This Concludes the Lab 8 Report.