EE 421L Digital Integrated Circuit Design Laboratory
Fall 2018, University of Nevada, Las Vegas

 

Student lab reports are found here.

  

Current grades are located here.

 

Lab Chips

Chip1_f18 – Nic, Marco, David  
Chip2_f18 – Victor, Daniel, Brian
Chip3_f18 – Michael, Rocky, Ethan
Chip4_f18 – Biruk, Franciso, Allis
Chip5_f18 – Jovanne, Esteban   
Chip6_f18 – Shadden, Dylan, James  
  

Project (not a group effort, each student will turn in their own project) – design a serial-to-parallel converter that takes 

serial input data and an associated clock signal and generates an 8-bit output (parallel) word and clock. 

The inputs to your circuit are Din and clock_in.

The outputs to your circuit are D0-D7 and clock_out.

If the serial input is 10 Mbits/s then the parallel output is 1.25 MWords/s.

First half of the project (just the serial-parallel converter schematics, no layout), of your design and an html report detailing 

operation (including simulations), is due at the beginning of lab on Nov. 14.  

Your serial-parallel design should show various inputs to verify it works

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu and link to your index.htm page.  

Dr. Baker will go over your design with you, including running simulations, when lab meets on Nov. 14.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 21.

Dr. Baker will meet with you on Nov. 21 to go over your layout and, again, put your report in the /proj folder in your directory at CMOSedu.  

Ensure that there is a link on your project report webpage to your zipped design directory.  

 

November 28 – Lab8 – Generating a test chip layout for submission to MOSIS for fabrication, due December 5
October 24 – Lab7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders, due November 7
October 10 – Lab6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder, due October 24
September 26 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 10   
September 19 – Lab4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process, due September 26 
September 12 – Lab3 – Layout of a 10–bit DAC, due September 19  
September 5 – Lab2 – Design of a 10–bit digital–to–analog converter (DAC), due September 12  
August 29 – Lab1 – Laboratory introduction, generating/posting html lab reports, installing and using Cadence, due September 5  
Watch the Lab Safety Training video and review the Lab Rules & Regulations here  
   

Instructor: R. Jacob Baker (see office hours at this link)

Lab Assistant: Luis Soriano (office hours: Wednesdays 9-11 AM and Thursdays 1-3 PM, office location: TBE B-310)    
Time: Wednesday from 11:30 to 2:15 PM

Course dates: Wednesday, August 29 to Wednesday, December 5

Location: TBE B–350

Holidays: none

Course content – Laboratory based analysis and design of digital and computer electronic systems.

Credits: 1

Corequisite: EE 421; Prerequisite: EE 320L

 

Grading
30% Quizzes
40% Lab Reports

30% Project
 

Policies 

  • Unlike the lectures, laptops can be used during the lab. Please bring your laptop with you to lab!
  • If a quiz is open book then only the course textbook can be used (no ebooks, Kindle, Nook, etc., older/international editions, or photocopies).
  • No late work accepted. Regularly being tardy for labs, leaving in the middle of labs, or leaving early is unacceptable without consent of the instructor.
  • Cheating or plagiarism will result in an automatic F grade in the lab
  • Questions for the instructor (only) should be asked in person (not via email). Do not email the instructor. 
  

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