Lab 7 - Rocky Gonzalez

Lab 07 - EE 421L

Authored by Rocky Yasuaki Gonzalez,

E-mail: gonzar14@unlv.nevada.edu

11/7/18

Lab 07: Using buses and arrays in the design of word inverters, muxes, and high–speed adders.

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Prelab:

The labs are backed up through a saved directory in my computer as well as into my google drive account (Up-to-Date from end of previous lab).

The prelab also demonstrates Tutorial 5 on the CMOSedu website. The image size can be increased by clicking on the images for more detail.

Tutorial 5 was read previously to provide insight for the design process for connecting a wire bus to an inverter..

The following lab will use similar techniques to recreate the logic gates for 8-bit devices.

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Lab:

Step 1: Make an equivalent, more concise, schematic by instantiating an inverter and naming the inverter using an arrayed name (I0<3:0> see image below).

Connect a wide-wire (bus) as seen below and connect it to input and output pins. Create a symbol for the schematic.

4-bit Inverter Symbol	Consise 4-bit Inverter Schematic	CMOS Inverter

Step 2: Using this symbol create a simulation schematic. All four inverters' inputs are tied together to an input pulse source.

-> The out<0> is not connected to a load while out<3> is connected to a 100fF load.

-> The out<1> is connected to a 1 pF load while out<2> is connected to a 500 fF load.

Show, in your lab report, how a capacitive load influences the delay and rise/fall times.

4-bit Inverter Simulation Schematic	4-bit Inverter Simulation Output

Based from the simulation output, we can see as the capacitive load increases on the output, the delay RC rise/fall increases.
This increase in time is not ideal for digital logic gates since we want our states to change from vdd to ground or ground to vdd instantaneously.

Step 3: Create schematics and symbols for an 8-bit input/output array of: NAND, AND, NOR, OR, and inverter gates.

	8-bit Symbol	Concise 8-bit Schematic	CMOS
NAND
AND
NOR
OR
Inverter

Provide a few simulation examples using these gates:

	8-bit Simulation Schematic	8-bit Simulation Output
NAND
AND
NOR
OR
Inverter

Step 3: Next examine the schematic of a 2-to-1 DEMUX/MUX (and create the symbol).
Simulate the operation of this circuit using Spectre and explain how it works.

Make sure to show, using simulations, how the circuit can be used for both multiplexing and de-multiplexing.

MUX/DEMUX Symbol	MUX/DEMUX Schematic

MUX/DEMUX SImulation Schematic	MUX/DEMUX Simulation Output

We can observe from the output simulation of the MUX that as the input Select is '1', 'A' becomes the active input and passes the output value.
In the same context, when the Select is set to '0', 'B' becomes the active input and passes the output value of the MUX.
Therefore, the logical operation 'Z = A*S + B*Si' is a suffice logical operation.
For a DEMUX operation, instead, the output is chosen to select the input line 'A' or 'B'.

Step 4: Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
Include an inverter in your design so the cell only needs one select input, S (the complement, Si, is generated using an inverter).
Use simulations to verify the operation of your design.

8-bit MUX/DEMUX Symbol	8-bit MUX/DEMUX Concise Schematic

8-bit MUX Operation Simulation Schematic	8-bit MUX Operation Simulation Output

8-bit DEMUX Operation Simulation Schematic	8-bit DEMUX Operation Simulation Output

Step 5: Finally, draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
Create an adder symbol for this circuit (see the symbol used in lab6). Use this symbol to draft an 8-bit adder schematic and symbol.
For how to label the bus so the carry out of one full-adder goes to the carry in of another full-adder review the ring oscillator schematic discussed in Cadence Tutorial 5. Simulate the operation of your 8-bit adder. Lay out this 8-bit adder cell. Show that your layout DRCs and LVSs correctly.

Full Adder Symbol	Full Adder (Alternative) Schematic

Full Adder (Alternative) Layout	Full Adder (Alternative) Extraction

The following images present the DRC and LVS succession for the single Full Adder schematic/extraction.

8-bit Full Adder Symbol	8-bit Full Adder Concise Schematic

8-bit Full Adder Layout:

8-bit Full Adder Extraction:

The following images present the DRC and LVS succession for the 8-bit Full Adder schematic/extraction.

The pins on the 8-bit layout are connected from 'Cn' to 'Cn+1' as shown:

8-bit Full Adder Operation Simulation Schematic	8-bit Full Adder Operation Simulation Output

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The design directory is downloaded from the MobaXterm server and backed up onto this website (Up-to-date 11/7/18).

-> They are stored into my backup folder on my laptop and also on my online drive.

The CMOSedu directory has been backed up, and my following lab design directories will be continued to become backe up.

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This Concludes the Lab 7 Report.

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