EE 421L – Digital IC Design Lab

 

Author: James Skelly

Email: James.Skelly@unlv.edu

Fall 2018

 

Labs

 

Lab 1

Lab 2

Lab 3

Lab 4

Lab 5

Lab 6

Lab 7

Lab 8

 

Project: Serial-to-Parallel Converter

 

 

 

Cadence Schematic Aesthetics Tutorial 

 

 

Return to EE 421L Students

Return to EE 421L Fall 2018 Page