EE 421L – Digital IC Design Lab – Lab 2
Email:
skellj1@unlv.nevada.edu
·
This lab covers the design of a 10-bit digital-to-analog (DAC)
converter.
Pre-Lab
·
Prior to coming to lab
make sure you understand how the input voltage, Vin, is related to B[9:0] and Vout (the quiz may
ask a question about this).
·
In your lab report: 1) provide
narrative of the steps seen above, 2) provide, and discuss, simulation results
different from the above to illustrate your understanding of the ADC and DAC,
3) explain how you determine the least significant bit (LSB,
the minimum voltage change on the ADC's input to see a change in the
digital code B[9:0]) of the converter. Use simulations to support your
understanding.
·
Backup your webpages and
design directory.
How is Vin related to B[9:0]
and Vout?
·
B[9:0] is a
10-bit binary representation of the value of the source Vin. The ADC receives
an analog input and converts that input into binary code. Each wire of the bus
(B[9:0]) represents a different digit of the 10-bit
binary representation of Vin, with B0 being the least significant bit and B9
being the most significant bit. This binary number is the output of the ADC and
is received by the DAC as binary code. The DAC takes the binary code and
converts it to an analog waveform, with its resolution being based on the
number of bits. This analog wave output is Vout, and
is a staircase waveform. The more bits we have, the more accurate of a
representation we will get of our input signal. Less bits would result in a far
less accurate representation of our input signal.
Narrative of Steps Taken to Complete Pre-Lab Part
1
1.)
Open the MobaXterm, sign into the Cadence server using the csimcluster.
2.)
Download lab2.zip to
desktop, upload to design directory, and add “DEFINE lab2 $HOME/CMOSedu/lab2” to cds.lib in MobaXterm
3.)
Change directories to the CMOSedu
directory
4.)
Type “Virtuoso &” to launch Cadence Virtuoso
5.)
To open the schematic:
a.
Open “lab2” library
b.
Open “sim_ideal_ADC_DAC” cell
c.
Open schematic view
6.)
Launch Analog Design Environment (ADE L)
7.)
To run simulation:
a.
In “Session” dropdown, select “Load State”
b.
Select “Cellview”, then “OK”
c.
Press green button to run
8.)
To edit plot:
a.
Right click background of graph, select “graph properties”
b.
Change background color to white
c.
Right click on a trace, select “trace properties”
d.
Change trace thickness, pattern, and color
Discussion of Different Simulations to Test
Functionality
·
In the simulation results above, as we can observe from the
waveforms, the output signal has a much greater number of incremental steps
than does the output waveform below. To achieve the simulation results below,
and to see the output steps more vividly, we can change the input voltage to an
amplitude of 10 mV with an offset of 10 mV, so that we can observe the height
of each step.
·
Placing markers at the lower trough of
the waveforms and at the height of the first step, we can observe that each step
has a height of 4.88 mV. This indicates that the Least Significant Bit (LSB) is
4.88 mV, because the least significant
bit is synonymous with the minimum
change on the ADC’s input required to see a change in the output B[9:0].
Determining the Least Significant Bit (LSB)
·
In order to find the
Least Significant Bit (LSB), from figure 30.14, we are given
·
Since VDD in our schematic is 5V, and the number of bits N=10, we
input these values above.
·
The least significant bit, or the minimum voltage change on the
ADC input to see a change in the digital code B[9:0]
is 4.883 mV.
·
By changing the properties of the voltage source so that the
amplitude of the waveform is half of the LSB voltage (2.44 mV) and the offset
is equal to the amplitude, we get the above simulation results, verifying that
4.88 mV is indeed the LSB.
Lab Tasks
·
Design a 10-bit DAC using an n-well resistor of 10k
·
How to determine the output resistance of the DAC (answer: R) by
combining resistors
·
Delay, driving a load
·
How to create a symbol view for your design with the exact same
footprint as the Ideal_10-bit_DAC symbol
·
Simulations to verify correct design functionality
Lab
Our DAC design
will be based on the topology below from figure 30.14 of the CMOS textbook.
Design of
10-bit DAC Using N-Well R of 10k
·
The resistive divider schematic
is drafted by instantiating three 10k resistors (2 in series, one in parallel
with the two in series), connecting them with wire, and adding pins to the
left, right, and bottom of the schematic. Once completed, select “create”, “cellview”, “from cellview”, and
create the symbol view of the schematic. I used the shape and dimensions of the
ideal DAC by copying and pasting.
Creating
Symbol View
·
By cascading ten of the symbols created in the previous step, we
can create the 10-bit DAC. The symbol for the 10-bit DAC was created using the
shape and dimensions of the given Ideal DAC symbol.
Finding
Resistance of 10-bit DAC
·
Beginning at the bottom, we have two 2R resistors in parallel. By
computing equivalent resistance of two identical resistors, we get Req=R. This
equivalent resistor is now in series with another R resistor. We are now back
where we began with two 2R resistors in parallel. Up the DAC to the B9 input,
we repeat the process and get a final Req of R.
Delay, Driving
a Load
·
By definition of an RC
circuit, we know that time delay is approximately 0.7RC. The circuit
constructed in this exercise, with a pulse voltage source feeding the DAC
(which has an equivalent resistance of R=10k) in series with a 10pF capacitor,
is effectively an RC circuit. We can therefore use the formula td = 0.7RC
to find the time delay of the DAC driving a load.
td = 0.7RC = 0.7*(10k)*(10p)
= 70ns
We see from the simulation results
that the time delay, or the time it takes for the voltage across the capacitor
to reach half of its maximum value, is approximately 69.5ns. Hand calculations
yielded a time delay of 70ns.
At 569.5ns, we observe an output
voltage of 1.25V, which is half of the maximum voltage across the capacitor
(2.5V). For visibility and clarity, the delay time of this simulation is 500ns.
At 500ns, the input voltage pulses to 5V, thus beginning to charge the
capacitor at the same instant. The time delay, then, is
td= 569.5 ns – 500 ns = 69.5 ns
JS DAC
Simulation, No Load
The JS DAC simulation above yields the
input voltage and the output voltage when there is no load connected to the
DAC. With no load, we observe the same waveforms that we received in the
simulation of the Ideal DAC in the prelab.
JS DAC
Simulation, 10k Resistive Load
Because the resistance of the DAC is 10k, when we connect a 10k load in series with the DAC, we get a voltage divider which cuts the voltage in half. We can observe this in the simulation results above, as Vin goes from 0 to 5V and Vout goes from 0 to 2.5V.
JS DAC Simulation,
10pF Capacitive Load
The capacitive load, as we see above
and will also see below, smooths the output wave. The capacitive load alone
also causes a DC offset of 2.5V on the output. We end up with an output wave
that oscillates between roughly 1V and 4V about the horizontal axis at 2.5V.
The output also lags the input by roughly 0.07 microseconds.
JS DAC Simulation,
R//C (Resistive and Capacitive) Load
The resistive and capacitive load
proves to give an output that is roughly half of the input (magnitude of voltage),
and the output lags the input slightly ( by roughly
0.05 microseconds).
Taking each of
the above simulations into consideration, we conclude that the output and input
are in phase when there is no capacitive component on the load. The no load and
resistive simulations result in the input and output being in phase. However, when
we add a capacitive component to the load, we get a delay, and the output lags
the input. When the load is strictly capacitive, the output lags further behind
the input than it does when the load is both capacitive and resistive.
·
In a real circuit, if the switch
resistance was not small compared to R, the equivalent resistance of the entire
DAC would not be R, and we would need to recalculate the resistance of the DAC
in order to match the load resistance and maximize the output with a load
connected.
- If you have
simulation convergence problems you can force the simulation to converge
by going to, in the ADE, Simulation -> Options -> Analog
- Set
the values as seen below
- relative
tolerance, reltol, of 10% (= 1e-1)
- voltage
absolute tolerance, vabstol, of 100 mV (=
1e-1)
- current
absolute tolerance, iabstol, of 1 mA (= 1e-3)
I did have problems with simulation convergence,
and needed to force the sims using the values above.
Backing Up Work
·
I zipped
up my lab 2 and dragged and dropped it into my google drive Cadence folder.
