EE 421L – Digital IC Design Lab – Lab 6
October 23,
2018
·
In this lab, we will design, layout, and simulate
a CMOS NAND gate, XOR gate, and Full-Adder.
Going Through Tutorial 4
·
In its entirety, tutorial 4 takes us through:
o Design of NAND
gate schematic
o Creating
symbol view of NAND gate
o Layout of NAND
gate
o Simulation of
NAND gate schematic
Shown here are
my completed simulation schematic (with my NAND symbol) and the NAND gate
layout.
Lab Tasks
- Draft the schematics of a
2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using
6u/0.6u MOSFETs (both NMOS and PMOS)
- Create layout
and symbol views for these gates showing that the cells DRC and LVS
without errors
- ensure that
your symbol views are the commonly used symbols (not boxes!) for these
gates with your initials in the middle of the symbol
- ensure all
layouts in this lab use standard cell frames that snap together
end-to-end for routing vdd! and gnd!
- use a standard
cell height taller than you need for these gates so that
it can be used for more complicated layouts in the future
- ensure gate
inputs, outputs, vdd!, and gnd! are all
routed on metal1
- Use cell names
that include your initials and the current year/semester, e.g.
NAND_jb_f19 (if it were fall 2019)
- Using Spectre simulate the logical operation of the gates
for all 4 possible inputs (00, 01, 10, and 11)
- comment on
how timing of the input pulses can cause glitches in the output of a
gate
- Your html lab
report should detail each of these efforts
- Below shows
(click for a larger image): 1) schematic of a 2-input NAND gate, 2)
schematic of a 2-input XOR gate, 3) simulation schematic, 4) example
pulse statement to generate a digital input, and 5) simulating the
operation of the gates for all 4 possible inputs.
- Using
these gates, draft the schematic of the full adder seen below
- Create a symbol for this full-adder (example)
- Simulate, using Spectre, the
operation of the full-adder using this symbol
- Layout
the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed
- full-adder inputs and outputs can be on metal2 but not
metal3
NAND Gate Construction
Shown
below are both the schematic view of the 2-input NAND gate, consisting of two
NMOS and two PMOS, all of width 6 microns, and length 600 nm, and the symbol
view of the NAND, as well.
Shown
below is the layout (and extracted) view of the NAND gate, constructed using
instructions from tutorial 4.
We see that the layout
DRC is successful and the LVS shows that the net lists match.
NAND Gate Simulation Results
XOR Gate
Construction
Shown here are the schematic of the 2-input XOR gate, and the symbol view of the XOR.
Shown here is the layout (and extracted view) of the XOR gate.
DRC
Verification and LVS Verification
XOR Gate
Simulation Results
Glitches (NAND and XOR Sims) are caused by the brief rise and fall times of the input signals. The glitch is simply a time period in which the pulse is rising or falling, and the MOSFETs are neither on, nor off, for that instant. If the rise/fall times were decreased, the glitches would become smaller and smaller. An ideal rise/fall time of 0 would result in no glitch.
Full Adder
Schematic and Symbol View
Full Adder
Simulation Results
Layout and
Extracted View of Full Adder
