EE 421L – Digital IC Design Lab – Lab 5
Email:
skellj1@unlv.nevada.edu
·
In this lab, we will design, layout, and simulate
a CMOS inverter.
Zipped-Up Lab 5 Directory
<<lab5.zip>>
Pre-Lab
Going Through Tutorial 3
·
In its entirety, tutorial 3 takes us through:
Shown here are
my completed simulation schematic (with my NOT symbol) and the inverter layout.
Lab Tasks
·
Draft schematics,
layouts, and symbols for two inverters having sizes of:
o
12u/6u (= width of the
PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
o
48u/24u where the
devices use a multiplier, M = 4
·
Example layouts are seen
below.
o
Notice that power is run
on the top of the cell via metal1 and ground is run on the bottom of the cell
also via metal1
o
Power (vdd!) is connected to the n-well using the ntap cell
o
Ground (gnd!) is connected to the p-substrate using the ptap cell
o
Running power and ground
with a single row of contacts, instead of 2 as seen below, is fine to reduce
layout size
o
Your schematics should
have two pins, e.g., A and Ai
o
Your layouts should have
4 pins: A, Ai, vdd!, and gnd! (note how lowercase
letters are used for power and ground)
o
Your lab reports should
document your efforts and results including showing that the extracted layouts
and schematics LVS correctly
o
Zip up these cells in a
directory call lab5_rjb.zip (last two or three letters are your initials) and
link to your lab report
·
Using SPICE simulate the operation of both of
your inverters showing each driving a 100 fF, 1
pF, 10 pF, and 100 pF capacitive load
- Comment, in
your report, on the results
·
Use UltraSim
(Cadence's fast SPICE simulator for larger circuits at the cost of accuracy)
and repeat the above simulations
- Use Setup -> Simulator/Directory/Host and select UltraSim as seen below
- You'll also have to point to the MOSFET models again
as seen below
- Note that UltraSim only performs transient simulations
(not AC, Noise, DC, operating point, etc.)
- Not knowing this last item will lead to wasted time
if trying to use UltraSim exclusively for
simulations
12u/6u Inverter (Width of PMOS / Width of NMOS)
Shown above are the schematic
of the inverter (left), along with the created inverter symbol view (right).
This inverter, as we can
see, has a multiplier of 1, or “1 finger”.
Above is the layout of
the (m=1) inverter (left) along with the extracted view (right).
We can also see that the
DRC and LVS verification was successful.
48u/24u Inverter (12u/6u with M=4)
Shown here are the schematic
and symbol view for the four finger inverter.
Here we can see that the
layout LVS and DRC verification was successful.
Simulation (100 fF to 100 pF Load,
Inverter m=1)
·
Rather than running four different
simulations, a parametric analysis was used to vary the capacitor from 100fF to
100pF.
·
We can observe from the
following simulations that as the capacitive load increases, the time it takes for
the inverter to respond to the input signal.
Spectre Simulation
UltraSim Simulation
Simulation (100 fF to 100 pF Load,
Inverter m=4)
Spectre Simulation
UltraSim Simulation
We can observe from the
simulations that the four finger inverter performs
better because the additional fingers or branches of the MOSFET allow the capacitor
to more efficiently charge and discharge.