EE 421L – Digital IC Design Lab – Lab 4
September 24,
2018
·
In this lab, we will generate the IV curves and
layout both NMOS and PMOS devices.
Pre-Lab
Going Through Tutorial 2
·
In its entirety, tutorial 2 takes us through:
o Schematic and
Layout of NMOS
o Schematic and
Layout of PMOS
o Test Circuit
and IV Curves of NMOS
o Test Circuit
and IV Curves of PMOS
Lab Tasks
·
Generate 4 schematics and simulations
o
A schematic for
simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1
V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n
width-to-length ratio.
o
A schematic for simulating
ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in
1 mV steps. Again use a 6u/600n width-to-length
ratio.
o
A schematic for
simulating ID v. VSD (note VSD not VDS) of a PMOS
device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies
from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length
ratio.
o
A schematic for
simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0
to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.
·
Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals
to probe pads (which can be considerably smaller than bond pads [see MOSIS design
rules] and directly adjacent to the MOSFET (so the layout is relative
small).
o
Show your layout passes DRCs.
o
Make a corresponding schematic so you can LVS your layout.
·
Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals
to probe pads.
o
Show your layout passes DRCs.
o
Make a corresponding schematic so you can LVS your layout.
Lab
Creating
Schematics/Symbol Views for NMOS/PMOS
·
Before beginning simulations, we needed
to create schematics and symbols for the transistors that we would be using.
NMOS
Schematic and Symbol
PMOS
Schematic and Symbol
ID
v. VDS of NMOS Device
·
In the first simulation, we let VDS vary
from 0 to 5V in 1mV steps, and we sweep VGS from 0 to 5V in 1V steps.
·
We also set the length of the NMOS to
600 nm, and the width to 6 microns.
Shown below
are the schematic and the IV curves of this NMOS with the given parameters.
ID v. VGS of NMOS Device
·
In the second simulation, we set VDS at
a constant value of 100mV, and we sweep VGS from 0 to 2V in 1mV steps.
·
We keep the same length and width of our
MOSFET, and instead of simulating ID v. VDS as we did previously, we simulate
ID v. VGS.
The schematic and IV curves are shown below.
ID
v. VSD of PMOS Device
·
The third simulation calls for a sweep
of VSG from 0 to 5V in 1V steps, and VSD should vary from 0 to 5V in 1 mV
steps.
·
The width of the PMOS is changed to 12
microns, while the length is kept at 600 nm.
·
Note that the base of the PMOS is tied
to VDD in this schematic. In the NMOS schematics, the base was tied to ground.
Below are
the schematic and the IV curves for the PMOS device.
ID
v. VSG of PMOS Device
·
For the final simulation, we set VSD to
100 mV and we sweep VSG from 0 to 2V in 1 mV steps.
Using the
same width and length of the previous MOSFET, we observe the results below.
Layout
of 6.0u/0.6u NMOS Device
Full Layout of NMOS Including Probe
Pads
Zoomed-In View of Layout of NMOS
Device, DRC, LVS Verification
Layout of 12.0u/0.6u PMOS Device
Full Layout of
PMOS Including Probe Pads
Zoomed-In View of Layout of PMOS
Device, DRC, LVS Verification
Backing Up Work
Zipped-Up lab
4 directory, placed in google drive.
