EE 421L – Digital IC Design Lab – Lab 7
Authored by James Skelly
Email:
skellj1@unlv.nevada.edu
October 26,
2018
Lab description
·
In this lab, we will use buses and arrays to design word
inverters, muxes, and high-speed adders.
Pre-Lab
Going Through Tutorial 5
·
In its entirety, tutorial 5 takes us through:
o Introduction
to instance arrays
o Schematic of
Ring Oscillator (31 NOT gates)
o Simulation of
Ring Oscillator
o Layout of Ring
Oscillator
Shown here are
my completed schematic and layout of the Ring Oscillator.
Lab Tasks
Create the array of four
inverters and simulate it.
Show, in your lab report,
how a capacitive load influences the delay and rise/fall times.
Create
schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND,
inverter, and OR gates.
Provide a few simulation examples using these
gates.
Create an
8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
Include an inverter in your design so the cell
only needs one select input, S (the complement, Si, is generated using an
inverter).
Use simulations to verify the operation of
your design.
Finally, draft the schematic of the full-adder
seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
Create an adder symbol for this circuit (see
the symbol used in lab6).
Use this symbol to draft an 8-bit adder
schematic and symbol.
For how to label the bus so the carry out of
one full-adder goes to the carry in of another full-adder review the ring
oscillator schematic discussed in Cadence Tutorial 5.
Simulate the operation of your 8-bit adder.
Lay out this 8-bit adder cell (*note* that
this is the only layout required in this lab).
Show that your layout DRCs and LVSs
correctly.
4-bit Inverter
Schematic and Symbol
4-bit Inverter
Simulation Results
For each of
the following gates, I have included four pictures:
·
The schematic of the gate
·
The symbol of the gate
·
The schematic of the 8-bit gate
·
The symbol of the 8-bit gate
8-Bit I/O Array of NOT Gate
8-Bit I/O Array of NAND Gate
8-Bit I/O Array of NOR Gate
8-Bit I/O Array of AND Gate
8-Bit I/O Array of OR Gate
Simulation of Logic Gates
·
To simulate the gates, I instantiated A and B square wave inputs
to act as truth table inputs for the gates.
o The LSB of each
of the gates’ output was branched off and plotted in the simulation.
o Instead of
providing a few simulations, all the gates were included in one simulation.
2:1 MUX
Simulation Results of 2:1 MUX
We can observe
from the simulation that:
·
When S is high, the output Z follows input A.
·
When S is low, the output Z follows input B.
Design of 2:1 MUX/DEMUX
Simulation Results of 2:1 MUX/DEMUX
From the MUX
simulation, we can observe that:
·
When S is high, the output Z follows input A.
·
When S is low, the output Z follows input B.
From the DEMUX
simulation, we can observe that:
·
When S is high, the input signal Y propagates through to C only.
·
When S is low, the input signal Y propagates through to D only.
2:1 MUX with Single Select Input
·
Instead of having individual inputs for S and Si, we connect an
inverter to the S input.
·
Tying the output of this inverter to the Si pin allows us to create
a MUX with a single select input.
Design and Simulation Results of 8-Bit MUX
From the 8-bit
MUX simulation, we see that:
·
When S is high, all 8 bits of output Z follow input signal A.
·
When S is low, all 8 bits of output Z follow input signal B.
AOI Full Adder
AOI Full Adder Schematic
·
Shown below is the AOI implementation of a full adder.
·
The schematic was drafted in Cadence based on figure 12.20 in the CMOS
book.
AOI Full Adder Symbol
8-Bit AOI Full Adder Schematic and Symbol
Simulation of 8-Bit AOI Full Adder (Adding Two
8-bit Binary Numbers)
In this
simulation, two 8-bit numbers were added to produce an 8-bit sum with no
carry-in.
·
B = 10000111 (binary) = 135 (decimal)
·
A = 00001111 (binary) = 15 (decimal)
·
S = 10010110 (binary) = 150 (decimal)
Layout of AOI Full Adder (with LVS Verification)
·
Shown below are layout and extracted views of the one-bit AOI full
adder.
·
We can see from the above photos that the DRC and LVS verifications
were successful.
Zoomed in Layout View of 8-Bit AOI Full Adder
Complete Layout of 8-Bit AOI Full Adder (with LVS
Verification)
·
Shown below are the layout and extracted views of the 8-Bit AOI
Full Adder.
·
From the above photos, we can see that the DRC and LVS verifications
were successful.