EE 421L – Digital IC Design Lab – Lab 3
September 11,
2018
Lab description
·
In this lab, we will layout the 10-bit DAC that we designed and
simulated in Lab 2.
Zipped-Up Lab 3 Directory
<<lab3.zip>>
Pre-Lab
Finishing Up Tutorial 1
·
In its entirety, tutorial 1 takes us through:
o Installation
of Cadence
o Set up of
libraries
o Drafting/simulating
a voltage divider schematic
o Creation of a
resistive divider symbol
o Layout of a
resistor
o Layout of a
resistive divider
o DRC of layout
o LVS of resistive
divider layout versus resistive divider schematic
The photos
below show the layout of the resistive divider, and the results of the LVS
verification.
Lab Tasks
·
Use the n-well
to layout a 10k resistor
o Discuss how to select width and length of the
resistor (reference process info from MOSIS)
·
Use this
resistor to layout a 10-bit DAC
o Discuss how the width and length of the resistor
are measured
·
Ensure that
each resistor in the DAC is laid out in parallel (the resistors are stacked)
·
All input and
output pins should be on metal 1
·
DRC and LVS
your design
·
Zip up final
design directory and place it in lab3 directory with a link to your lab report
Lab
Layout of 10k Resistor
using N-Well
From the MOSIS parameters file for ami-C5 (the C5 process), we see that for
n-well, sheet resistance is 796 ohms/sq.
The minimum length of n-well is 12 lambda. Above,
we observe lambda=0.30 um, or 300 nm. Our minimum length of n-well is then 3.6
um.
Selecting Length and Width
If we use the minimum length of n-well (3.6 um) as the width of our
resistor, given that we want to achieve R = 10k, and we know from the C5
process that the sheet resistance of n-well is 796 ohms/sq,
we can calculate our desired length by
Measuring Length and Width
However, we need our length to be a multiple of lambda. For this reason,
we will use a length of 45.3 um, or 151 lambda. In
doing so, we run our DRC, and there are no errors.
We can measure the length and width of the resistors (in mils) by
pressing “k” to create a ruler.
After extracting the layout and achieving a resistance of 10.31k, we can backsolve to find the true value of Rsquare in cadence.
We can then recalculate our length using the newly calculated Rsquare, the minimum width 3.6um, and our desired 10k
resistance.
But, since 43.9 is not a multiple of lambda, we will use 43.8 um for our
length. Redrawing the n-well resistor to have length 43.8 um and width 3.6 um,
our extracted view gives us a resistance of 9.964k, much closer to 10k than our
previous 10.31k.
Layout of DAC
Using 10k N-Well Resistor
When I first simulated the array of resistors, markers were placed
between each of the resistors, marking n-well spacing errors. The minimum
requirement for space between n-well, as is shown to the left, is 5.4 microns.
After receiving the error, I spaced my resistors by 5.4 microns all the way
down the array.
After wiring the resistors:
When we LVS the extracted view of the layout and the schematic of the DAC
we created in lab 2,
we see from the output of the simulation that the net lists match, and the LVS is successful.
Pictured here is the extracted view of the layout, which shows the
resistive property of each n-well resistor.
As we saw earlier, the resistance of each is 9.96k.
Simulation of DAC output from Lab 2
