EE 421L - Digital Electronics Lab
| Lab 1 | Laboratory introduction, generating/posting html lab reports, installing and using Cadence |
| Lab 2 | Design of a 10–bit digital–to–analog converter (DAC) |
| Lab 3 | Layout of a 10–bit DAC |
| Lab 4 | IV characteristics and layout of NMOS and PMOS devices in ON's C5 process |
| Lab 5 | Design, layout, and simulation of a CMOS inverter |
| Lab 6 | Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adders |
| Lab 7 | Using buses and arrays in the design of word inverters, muxes, and high–speed adders |
| Lab 8 | Generating a test chip layout for submission to MOSIS for fabrication |
| Project | Design an even parity checking circuit that checks a 9-bit input word, 8-bits data and 1-bit parity and outputs a 1 (0) when the even parity check is valid (invalid) |