Lab 7 -
EE 421L
Authored
by Reiner Dizon,
Email: dizonr1@unlv.nevada.edu
Today's
date is November 7, 2017
Lab
description: This
lab is about using buses and arrays for inverters, muxes, and adders.
PRELAB
- Back-up all of my work from the lab and the course
Lab Backup:
![Click for image prelab/prelab_1_backup_lab.PNG](prelab/prelab_1_backup_lab.PNG) | Course Backup:
![Click for image prelab/prelab_2_backup_class.PNG](prelab/prelab_2_backup_class.PNG)
|
Tutorial 5 is about the design of a 31 ring oscillator.
Here are the original and simplified schematic (using wide bus) for this design which will be used for LVS later:
I then ran
simulation on both schematics with initial conditions and models loaded in, and their simulations are identical.
I laid out the ring oscillator and DRCed it. Since the
schematic and layout were already created, I performed LVS afterwards to
confirm if the netlists matched.
Here is the schematic symbol for the ring oscillator:
Finally,
I ran the
simulation on both the schematic and the layout, and the simulations
were identical. For the simulating the NAND gate schematic, I created a
simulation schematic with power and ground.
Simulation Schematic:
![prelab/prelab_10_sim_sch.PNG](prelab/prelab_10_sim_sch.PNG)
Simulation Results (Schematic):
![prelab/prelab_12_sim_sch_wave.PNG](prelab/prelab_12_sim_sch_wave.PNG)
Simulation Results (Extracted):
![prelab/prelab_11_sim_ext_wave.PNG](prelab/prelab_11_sim_ext_wave.PNG)
- Read through the lab before starting
LAB
REPORT
1) Create a 4-bit Inverter
In
order to simplify circuit design for 4 inverters, I made a concise
schematic with the use of wide bus and instantiate an array of the
inverters. Here are my schematic and symbol:
Concise Schematic:
![postlab/1_inverter4x_sch.PNG](postlab/1_inverter4x_sch.PNG)
| Symbol:
![postlab/1_inverter4x_symbol.PNG](postlab/1_inverter4x_symbol.PNG)
|
I
simulated the inverters with different capacitive loads to observe the
rise and fall times. I observed that the delay increases as the
capacitance of the load increases. Here are my simulation schematic and waveform:Simulation Schematic:
![postlab/1_inverter4x_sim_sch.PNG](postlab/1_inverter4x_sim_sch.PNG)
| Simulation Waveform:
![postlab/1_inverter4x_sim_wave.PNGpostlab/1_inverter4x_sim_wave.PNG](postlab/1_inverter4x_sim_wave.PNG)
|
2) Create a 8-bit Inverter, NAND, XOR, AND, NOR, and OR gates
Gate Name | Concise Schematic | Symbol | Simulation Waveform |
NOT | ![postlab/2_inverter8x_sch.PNG](postlab/2_inverter8x_sch.PNG) | ![postlab/2_inverter8x_symbol.PNG](postlab/2_inverter8x_symbol.PNG) | ![postlab/2_inverter8x_sim_wave.PNG](postlab/2_inverter8x_sim_wave.PNG) |
NAND | ![postlab/3_nand8x_sch.PNG](postlab/3_nand8x_sch.PNG)
| ![postlab/3_nand8x_symbol.PNG](postlab/3_nand8x_symbol.PNG)
| ![postlab/3_nand8x_sim_wave.PNG](postlab/3_nand8x_sim_wave.PNG)
|
XOR | ![postlab/4_xor8x_sch.PNG](postlab/4_xor8x_sch.PNG)
| ![postlab/4_xor8x_symbol.PNG](postlab/4_xor8x_symbol.PNG)
| ![postlab/4_xor8x_sim_wave.PNG](postlab/4_xor8x_sim_wave.PNG)
|
AND | ![postlab/5_and8x_sch.PNG](postlab/5_and8x_sch.PNG)
| ![postlab/5_and8x_symbol.PNG](postlab/5_and8x_symbol.PNG)
| ![postlab/5_and8x_sim_wave.PNG](postlab/5_and8x_sim_wave.PNG)
|
NOR | ![postlab/6_nor8x_sch.PNG](postlab/6_nor8x_sch.PNG)
| ![postlab/6_nor8x_symbol.PNG](postlab/6_nor8x_symbol.PNG)
| ![postlab/6_nor8x_sim_wave.PNG](postlab/6_nor8x_sim_wave.PNG)
|
OR | ![postlab/7_or8x_sch.PNG](postlab/7_or8x_sch.PNG)
| ![postlab/7_or8x_symbol.PNG](postlab/7_or8x_symbol.PNG)
| ![postlab/7_or8x_sim_wave.PNG](postlab/7_or8x_sim_wave.PNG)
|
Here is the simulation schematic for all of the simulations of all the gates:
3) Create a 2-to-1 DEMUX/MUX
Concise Schematic:
![postlab/8_mux_sch.PNG](postlab/8_mux_sch.PNG)
| Symbol:
![postlab/8_mux_symbol.PNG](postlab/8_mux_symbol.PNG)
|
Simulation Schematic:
![postlab/8_mux_sim_sch.PNG](postlab/8_mux_sim_sch.PNG)
| Simulation Waveform:
![postlab/8_mux_sim_wave.PNG](postlab/8_mux_sim_wave.PNG)
|
4) Create an 8-bit wide 2-to-1 DEMUX/MUX
Concise Schematic:
![postlab/9_mux8x_sch.PNG](postlab/9_mux8x_sch.PNG)
| Symbol:
![postlab/9_mux8x_symbol.PNG](postlab/9_mux8x_symbol.PNG)
|
Simulation Schematic:
![postlab/9_mux8x_sim_sch.PNG](postlab/9_mux8x_sim_sch.PNG)
| Simulation Waveform:
![postlab/9_mux8x_sim_wave.PNG](postlab/9_mux8x_sim_wave.PNG)
|
5) Create an 8-bit Full Adder
Concise Schematic:
![postlab/10_full_adder_8x_sch.PNG](postlab/10_full_adder_8x_sch.PNG)
| Symbol:
![postlab/10_full_adder_8x_symbol.PNG](postlab/10_full_adder_8x_symbol.PNG)
|
Layout (Full)
| ![postlab/10_full_adder_8x_layout_full.PNG](postlab/10_full_adder_8x_layout_full.PNG)
|
Layout (Left)
| ![postlab/10_full_adder_8x_layout_in.PNG](postlab/10_full_adder_8x_layout_in.PNG)
|
Layout (Right)
| ![postlab/10_full_adder_8x_layout_out.PNG](postlab/10_full_adder_8x_layout_out.PNG)
|
DRC Results:
![postlab/10_full_adder_8x_drc.PNG](postlab/10_full_adder_8x_drc.PNG)
Extracted (Full)
| ![postlab/10_full_adder_8x_extracted_full.PNG](postlab/10_full_adder_8x_extracted_full.PNG)
|
Extracted (Single)
| ![postlab/10_full_adder_8x_extracted_single.PNG](postlab/10_full_adder_8x_extracted_single.PNG)
|
LVS Results:
![postlab/10_full_adder_8x_lvs.PNG](postlab/10_full_adder_8x_lvs.PNG)
Simulation Schematic:
![postlab/10_full_adder_8x_sim_sch.PNG](postlab/10_full_adder_8x_sim_sch.PNG)
Simulation Waveform (Schematic):
![postlab/10_full_adder_8x_sim_wave_sch.PNG](postlab/10_full_adder_8x_sim_wave_sch.PNG)
| Proof:
![postlab/10_full_adder_8x_sim_wave_sch_proof.PNG](postlab/10_full_adder_8x_sim_wave_sch_proof.PNG)
|
Simulation Waveform (Extracted):
![postlab/10_full_adder_8x_sim_wave_extracted.PNG](postlab/10_full_adder_8x_sim_wave_extracted.PNG)
| Proof:
![postlab/10_full_adder_8x_sim_wave_extracted_proof.PNG](postlab/10_full_adder_8x_sim_wave_extracted_proof.PNG)
|
After finishing the lab, I backed up my lab 7 web directory from CMOSedu and library from the cluster:
![Click for image postlab/postlab_backup.PNG](postlab/postlab_backup.PNG)
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