Lab 3 - EE 421L 

Authored by Reiner Dizon,

Email: dizonr1@unlv.nevada.edu

Today's date is September 13, 2017

  

Lab description:

This lab will focus on layout design for the 10-bit DAC from last lab. For the prelab, I finished the rest of Tutorial 1 and backed up all of my work for the lab and the lecture both from the csimcluster and the website.

PRELAB

 
Backup of previous lab:
prelab_1_backup.PNG
 
All other related files are all backed up in OneDrive, as well:
prelab_2_backup_all.PNG
 

LAB REPORT

 
How to select the width and length of the resistor: The sheet resistance of the n-well from MOSIS's information is about 800 ohms/square. With this information, we can determine the required length of a 10k n-well resistor assuming that the width is 4.5 microns. The calculation for length is as follows:postlab_eqn.PNG

With these specifications, here is the n-well layout for the 10k resistor (with 2 n-taps) as specified from Tutorial 1:
postlab_1_10k_layout.PNG
 
Here is the property of the n-well:
postlab_0_measured.PNG
 
How the width and length of the resistor are measured: To measure for these sizes, use the ruler tool in the layout program by clicking Tools => Create Ruler or by pressing the key binding "K". Here is a use of the tool in my n-well layout:
postlab_2_10k_ruler.PNG
 
 

After creating this n-well resistor layout, a Design Rule Check tool is used to determine if the design follows the rules for the process we are using. After successful check, the resistance value can be shown by extracting the layout which will show the value based on specifications of the process.

postlab_3_10k_extracted.PNG

 

As seen above, the resistance of this n-well resistor is about 10.21K ohms.

 

 

Layout View: This n-well resistor layout is the foundation to create the 10-bit DAC using 10k resistor. Here is my design of the 10-bit DAC and DRC results:

 

postlab_4_DAC_layout.PNG
Zoomed In (at the bottom):
postlab_5_DAC_layout_zoom.PNGpostlab_5_DAC_layout_zoom.PNG
 
DRC Results:
postlab_6_DRC.PNG

 

Extracted View: After finishing the layout, I extracted the layout to see the resistor values again and to compare it to the schematic using LVS.

 

postlab_8_DAC_extracted.PNGZoomed In:
postlab_9_DAC_extracted_zoom.PNG

Extracted Results:

postlab_7_extract_msg.PNG

 

Layout vs. Schematic (LVS): With the extracted layout, I can now compare the layout to the schematic from lab 2.

postlab_10_LVS_window.PNG

 

Results:

postlab_11_LVS_good.PNG

Link to LVS Output

Link to Design Directory Zip File

 

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