Lab 8 - EE 421L 

Reiner Dizon, dizonr1@unlv.nevada.edu

Angel Solis, solisa1@unlv.nevada.edu

John Dye, dyej1@unlv.nevada.edu

Today's date is December 6, 2017

  

Lab description: This lab is about the generation of test chip layout for submission to MOSIS for fabrication.

 

DESIGN DIRECTORY:

Chip1_f17.zip


CHIP CONTENTS

CHIP SCHEMATIC
pictures/chip_sch.png

CHIP LAYOUT

pictures/chip_lvs.PNG

PIN CONNECTIONS

 
Ring Oscillator
pictures/ring_osc.png
PinConnection
Pin<1>VDD
Pin<2>osc_out
 
 
NAND Gate
pictures/nand.png
PinConnection
Pin<21>VDD
Pin<22>A
Pin<23>B
Pin<24>AnandB
 
 
NOR Gate
pictures/nor.png
PinConnection
Pin<36>AnorB
Pin<37>B
Pin<38>A
Pin<39>VDD
 
 
XOR Gate
pictures/xor.png
PinConnection
Pin<3>AxorB
Pin<4>B
Pin<5>A
Pin<6>VDD
 
 
Inverter Gate
pictures/inverter.png
PinConnection
Pin<14>VDD
Pin<15>In
Pin<16>Out
 
 
PMOS Transistor
pictures/pmos.png
PinConnection
Pin<10>Source
Pin<11>Gate
Pin<12>Drain
Pin<13>Body
 
 
NMOS Transistor
pictures/nmos.png
PinConnection
Pin<7>Drain
Pin<8>Gate
Pin<9>Source
Pin<20>Body (gnd!)
 
 
Resistive Divider
pictures/resist.png
PinConnection
Pin<17>25K in
Pin<18>25K to 10K
Pin<19>10K in
 
 
Even Parity Checker Circuit
pictures/parity.png
PinConnection
Pin<25>D0
Pin<26>D1
Pin<27>D2
Pin<28>D3
Pin<29>D4
Pin<30>D5
Pin<31>D6
Pin<32>D7
Pin<33>P
Pin<34>check
Pin<35>VDD
 
 
 

 

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