ECE 421L - Digital Integrated Circuit Design Laboratory
Jalen Solis
Email: solisj8@unlv.nevada.edu
Labs:
Lab1: Cadence Tutorial
Lab2: Design of a 10-Bit Digital to Analog Converter
Lab3: Layout of a 10-Bit DAC
Lab4: IV Characteristics and Layout of both NMOS and PMOS Devices using the C5 Process
Lab5: Design, Layout, Simulation of a CMOS Inverter
Lab6: Design, Layout, and Simulation of a CMOS NAND Gate, XOR Gate, and Full-Adder
Lab7: Design of Word Inverters, Muxes, and High-Speed Adders
Lab8: Generating a Test Chip Layout for Fabrication
Lab Project: Design, Layout and Simulation of a Non-Inverting Buffer Circuit
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