Lab 8 - ECE 421L 

Authored by: Jalen Solis (solisj8@unlv.nevada.edu), Martin Mercado (mercam13@unlv.nevada.edu), Larri Gomez (gomezl6@unlv.nevada.edu)

   

December 6, 2023

     

The purpose of this lab is to create a chip using circuits made in previous labs. The first part of the lab requires all students to complete tutorial 6, this tutorial teaches students how to layout a pad, padframe, and chip within Cadence. Using what was learned from the tutorial, students will form into groups of 3 to put test structures onto a chip. Each test circuit will have its own power but the ground will be shared between all circuits. 

     

The following circuits will be put onto the chip and tested:

   

 Prelab


   

Before we start the prelab, it is important to back up all the work that was done in previous labs:

pl0

   

The first step in the prelab is to create the layout of a single pad:

pl1

   

Once the single pad is created the next thing to do is to create a padframe that has a total of 40 pads

   

A new layout will be created called "padframe" and will need the single pad that was created previously:

pl15pl2

   

The pad layers can then be removed an the length and width of the chip can be measured:

pl3

   

Now that the chip has been created the next part is to create the schematics

   

Pad:

pl4

pl5

   
Pad Frame:

pl7

pl8

   

With the chip ready for layout we can use several circuits that were made from previous labs and implement them into the design:

pl9

   

With the schematic completed for the chip the layout can be started:

pl10

   
Layout of Inverter and NMOS:

   

pl11

   

Layout of NMOS and Voltage Divider:

   

pl12
   
Layout of Ring Oscillator and common VDD pin:
   
pl13
   
Layout of NAND Gate and common GND pin:

     
pl14

   

The layout can then be saved and this concludes the prelab

   

Lab


   

Using what was learned from the prelab we can create our own chip and place several circuits that we've made including some projects.

   

The first thing to do is to place all the circuits that will be on the chip in a schematic:

l1

   

Once the schematic is created we can move on to the symbol of the chip:

l2

   

Now that the symbol is completed out we can create the layout of the circuit:

   

l3

   

l4
  1. PMOS
  2. Inverter
  3. NMOS
l5
   
     4. NOR Gate
     5. NAND Gate

     
l6
   
     6. Ring Oscillator
     7. Synchronous SPS Buck Converter

     
l7
   
     8. Voltage Divider
     9. 25k N-Well Resistor
     10. Non-Inverting Buffer

     

With our chip fully laid out, we can run some simulations on the chip to make sure it is functioning correctly:

l8

     

  1. Find out what pins are connected to the input, output and supply power of the circuit
  2. Place the power supply down and connect a wire to the pin associated with it
  3. Connect ground to pin 20
  4. Connect the input to the correct pin (Voltage Divider = pin 22, Non-Inverting Buffer = pin 26)
  5. Connect the output to the correct pin (Voltage Divider = pin 23, Non-Inverting Buffer = pin 28)
  6. Check & Save design (can ignore floating points or attach noConn)
  7. Open ADE L, select, and plot outputs
      l9
     
After running the simulations we see that our chip functions correctly
   
We can also run simulations of the other circuits to see if they work:
   
NOR:

l10
     
Inverter:
l11
   
PMOS:
l12
     
NMOS:
l13
     
NAND:
l14
     
25k N-Well Resistor:
l15
     
Ring Oscillator:
l16
     
This concludes the lab
     
With the completion of lab 8 we can zip up our folder and back up our work:
l17
     
Lab 8 File: Chip5_f23.zip

   

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