Lab 6 - ECE 421L 

Authored by Jalen Solis,

October 25, 20223

Prelab

The purpose of the prelab is to become familiar with the design, layout, and simulation of a CMOS NAND gate. The completion of this prelab will be beneficial for the actual lab as the lab inolves using a NAND gate.

Before we can start the prelab we must back up our work:

• We will do this by backing up our work in the Dropbox

First we will create a library named "Tutorial 4":

• We need to make sure we attach the AMI 0.60u C5N process before we create the library

Now we will create the cell view for the NAND gate:

Using skills we learned from previous labs, we can create the schematic view for the NAND gate:

• Our inputs will be "A" and "B"
• Our outputs will be "AnandB"

With our schematic made we can create the symbol view for it:

Next we can create another schematic to simulate the NAND gate:

• We can name our cell view "sim_nand2"

• Capacitor will be 100 fF
• We need to make sure we check and save the schematic
  

Our voltage source will be a pulse from 0V to 5V:

• Delay is 10 ns
• Rise and Fall time is 1ns
• Pulse width is 20 ns
• Period is 40 ns

We need to make sure both the PMOS and NMOS model libraries are selected:

In order to make the vdd output a voltage we must create a stimuli of 5V:

We will select the outputs to be plotted and run the simulation for 100 ns:

The voltage source of vdd is always at 5V:

• We see that when the pulse voltage and vdd are 5V the output is 0V or "off"
• When vdd and the pulse voltage differ the output is 5V or "on"

• First we must layout the PMOS, NMOS, NTAP, PTAP

We can then connect the NMOS and PMOS with the poly and create pins at each terminal:

Since we dont need the middle section between the two NMOS's we can remove it by flattening:

We can now connect the MOSFET's together and create a pin for the output and DRC the layout:

We can then extract the layout:

We can start the LVS:

We see that the netlists match:

This completes the prelab

Lab

The purpose of this lab is to use what was learned from the prelab to design, layout, and simulate a CMOS XOR gate. This XOR gate along with the NAND gate will be used to create a Full-Adder.

The first thing we need to do is create a schematic for an inverter, NAND gate, and XOR gate so that we can simulate all three to see the effects of the inputs on the outputs. 

We can first create a schematic for the inverter:

• We need to make sure to check and save the schematic

Then we can create a symbol view for the inverter:

• We will use an initial to classify the inverter is ours

Next we can create a layout for the inverter:

• We need to DRC the layout to check for errors

Now we can extract the layout:

Finally we can LVS the layout:

Next we need to create the NAND gate:

• Making sure to check and save the schematic

We can follow what we did in the prelab to create the layout of the NAND gate:

• Making sure to DRC our layout to check for errors

The layout can now be extracted:

We see that our netlists match:

• The XOR gate utilizes two inverters that are 6u/0.6u on the left side
• The right side uses 4 PMOS's and 4 NMOS's
• Once the XOR gate is created we can check and save the design

Now we can create the symbol view of the XOR gate:

• Making sure to DRC the layout to check for errors

Once we DRC the layout we can extract it:

We can then LVS the layout:

We see that the net lists match:

With all our gates created we can run a simulation:

• Making sure to check and save the schematic

The first pulse voltage will run a pulse width of 200 ns and a period of 400 ns:

The second pulse voltage will run a pulse width of 100 ns and a period of 200ns:

• The second pulse run at 2x the speed of the first pulse voltage so that we can ge the inputs of  00, 01, 10, 11

We need to always make sure that we have both model libraries set up:

We will run the simulation for 500 ns:

We see that all the gates work correctly with the two inputs:

• We see that the output of the XOR gate briefly drops for a moment before going back up
• This is because the rise and fall times do not happen instantly
• When the input switches from 01 to 10 the output of goes to 0 for a moment before going back up
• This is either because the input A is delayed so that the inputs is 00 or the B input is delayed and the input is 11

• Making sure to check and save the schematic

With our schematic free of errors we can create a symbol view of the full-adder:

Now we can create the layout of the full-adder:

• The layout is created with 3 NAND gates and 2 XOR gates
• The inputs and outputs of the layout are made using the metal2 layer
• Once made we need to run the DRC to check for errors

Now we can extract the layout:

Now we can set up and run the LVS:

We see that the netlists match:

Finally we can run a simulation on the full-adder:

• Making sure to check and save the schematic

The first pulse will run a pulse width of 200 ns and a period of 400ns:

The second pulse will be 2x faster than the first pulse:

• Pulse width = 100 ns
• Period = 200 ns

The third pulse will be 2x as fast as the second pulse and 4x as fast as the first pulse:

• The pulse widths and periods are set so that the inputs of 000, 001, 010, 011, 100, 101, 110, 111 can be created

We will run our simulations for 500 ns:

• We can set our inputs and outputs to be measured

Running the simulations we see that the full-adder works correctly:

• We see that there are sudden drops and spikes
• This is because the rise time and fall times do not happen instantly
• Since they do not happen instantly the output is detected as a different input then is what is desired
• When the inputs switch from 001 to 010 there is a delay when switching so the inputs can briefly read as 000 and cause the output to go to 0 for a brief moment

This completes the lab

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