Lab

Lab 2 - ECE 421L

Authored by Jalen Solis, solisj8@unlv.nevada.edu

September 6th, 2023

Prelab

In this weeks lab we will be going over the design of a 10-bit digital-to-analog converter (DAC)

Having already downloaded the lab2.zip file, we will need to sign into Cadence in order to unzip it:

pl1

We will then need to upload the zip file into the CMOSedu directory:

pl2

We then use the command window to enter into the CMOSedu directory and use the unzip command to unzip the folder:

pl3

To verify, we can see that the unzipped folder is shown on the left side of the screen:

pl4

We then need to enter the cds.lib file within the CMOSedu folder and enter the text "DEFINE lab2 $HOME/CMOSedu/lab2" as this will set up the library we need:

pl5

We can now launch virtuoso and enter the library manager where we can see that the library for lab 2 was made along with the cells for it.

For this prelab we will be focuing on the cell "sim_Ideal_ADC_DAC"

We can now view the schematic:

We can then load up the analysis we want for this schematic along with the desired output we want to be plotted:

Plotting the schematic we can see that the inputted sine wave has now been transformed from an analog signal to a digital signal and then back to an analog signal:

Changing Reference Voltage to 4V

We can see that if the reference voltage is lowered from 5V to 4V the output voltage Vout is cut at 4V: pl12

In order for the ADC to output a binary value it must compare the current Vin voltage with a calculated voltage which involves multiplying the referece voltage with the most significant bit and dividing it by 2^n where n is the number of bits:

pl13

This value is then compared with the current Vin voltage:

2V < 3V

If Vin is bigger than calculated value then the most significant bit is kept at 1
If Vin is smaller than the calculated value then the most significant bit is changed to 0

This repeats until all bits have been called

The problem with setting the reference voltage lower than the peak amplitude is that any Vin voltage past 4V will always result in all the bits being 0

This means that the output voltage is kept the same until the input voltage is lowered past 4V

Setting the reference voltage higher than 5V will not do anything because the peak amplitude of the input voltage can only max out at 5V therefore doing the comparison will always result in

Increasing Clock Period

As we increase the period on the clock we can see that Vout becomes less precise as there is a higher difference between Vin and Vout:

pl14

Decreasing Clock Period

As we decrease the period on the clock we can see that Vout has become more precise however, we also see that Vout has become less accurate:

pl15

Calculating LSB

The LSB or least significant bit of the converter can be calculated by dividing the reference voltage by the maximum number that can be obtained by the amount of bits.

pl10

We can then see that the least significant bit of the converter is 4.883 mV

Plotting the value of the LSB on Vout we can see that it falls on the rising edge. This is the first rising edge of the period from 0V to 5V and we can observe that anything below 4.883 mV is going to have a value of 0:

Lab

In this lab we will focus on designing a voltage-mode 10-bit DAC without an op amp. We will mimic most of the symbols used in the Ideal_DACbit schematic in order to keep the design looking clean and organized.

Creating Voltage-Mode 10-bit DAC without an Op-Amp

Looking at the voltage-mode DAC, we can see that it is comprised of many resistors. We can also see that the DAC has a repeating pattern all the way up to bit 1 which consists of 2R and R:

Our first step will be to create a schematic for this section of the DAC:

For the resistors we will use 10k and each 2R will consist of two 10k resistors:

After adding pins for the inputs and outputs we can check & save our schematic and create a symbol for it:

We can see that the pins from the schematic match the symbol
This symbol will be used nine times for the bits 1-9

Next, we need to focus on the bottom section of the DAC as it uses two 2R instead of a 2R and R:

We will follow the same process, the only difference is the bottom has two 10k resistors and is connected to ground:

After connecting pins to the inputs and outputs as well as running the check & save we can turn the schematic into a symbol:

This symbol will only be used at the bottom of the DAC for bit 0

Once we have both symbols we can create another schematic where we can use the newly made symbols:

We can see that we start out with the highest bit and go down to the lowest bit, similar to the figure
Our inputs for the schematic will be B9-B0 and our output will be v_out

We again, add inputs and outputs to our schematic and run the check & save so that we can turn it into another symbol:

We can see that our symbol that we created closely matches the one from the prelab

Testing Fully Built 10-bit DAC

Once we have our fully built DAC we can test it by using the sim_Ideal_ADC_DAC from the prelab:

We will need to delete the given DAC and replace it with our own

Running the transient analysis from 0 to 1u seconds we can see that the Vout from the DAC we designed matches the Vout from the DAC used in the prelab:

10-bit DAC given from prelab:

pl9

Voltage-mode 10-bit DAC without an op-amp:

l16noload

Testing 10-bit DAC Under Different Loads

Connecting a resistive load of 10k we can see that the amplitude is cut in half from 5V to 2.5V:

This is because the output resistance is 10k and when we connect a 10k resistive load the circuit acts as a voltage divider
Voltage divider formula is Vout = Vin * ( 10k / 10k + 10k ) if Vin = 5V then Vout = 2.5 V

Connecting a capacitive load of 10pF we can see that the output voltage becomes delayed, the amplitude shrinks and the sine wave becomes more smooth:

l9Cload

Connecting both a resistive load of 10k and a capacitive load of 10p F we can see that the sine wave becomes more smooth, the output becomes delayed, the amplitude decreases by 0.5 from the resistor and then some more by the capacitor:
l11RCload

Output Resistance of DAC

Here we can calculate the output resistance of the DAC:

l20

Delay of DAC

Here we run the hand calculations to see what the delay will be:

Next, we will ground all bits except bit-9. For this bit we will connect a pulse that ranges from 0V to 5V and measure the output when we connect a capacitive load of 10p F:

l18

l17

Physical Applications of DAC:

In a real circuit, the switches that are used within the figure are implemented with transistors, more specifically MOSFET's. These carry a small resistance and it isn't enough to disrupt the DAC. If these switches are not small compared to the resistors used in the figure then it will add to the overall resistance of the circuit causing 2R to become 2.5R or 3R. This means that the resistive output will increase the further we go up in bits instead of staying the same.

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