Digital Integrated Circuit Design - ECE 421L

Taught by Professor: R. Jacob Baker, PhD, PE

Authored by Edgar Rodriguez Nevares

Email: rodrie27@unlv.nevada.edu  

"sunrise, parabellum: un jour je serai de retour près de toi"

Labs:

Lab 1: Cadence Introduction

Lab 2: Design of a 10-bit digital-to-analog converter (DAC)

Lab 3: Layout of a 10-bit DAC

Lab 4: IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

Lab 5: Design, Layout, and Simulate a CMOS inverter

Lab 6: Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder

Lab 7: Using buses and arrays in the design of word inverters, muxes, and high–speed adders

Lab 8: Generating a test chip layout for fabrication