Labs - ECE 421L
Authored by Xavier Hernandez
hernax1@unlv.nevada.edu
Lab Links
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Lab 1 - Cadence Introduction and Generating html reports
Lab 2 - Design of a 10-bit Digital-to-Analog Converter
Lab 3 - Layout of a 10-bit Digital-to-Analog Converter
Lab 4 - IV Characteristics of NMOS and PMOS devices in ON's C5 process
Lab 5 - Design, Layout, and Simulation of a CMOS inverter
Lab 6 - Design, Layout, and Simulation of a CMOS NAND, XOR and Full-Adder
Lab 7 - Using Busses and Arrays in the Design of Word Inverters, Muxes, and High Speed Adders
Lab 8 - Generating a test chip layout for fabrication
Project
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