Lab 6 - ECE 421L 

Authored by Xavier Hernandez, hernax1@unlv.nevada.edu

10/25/23

Prelab

For this prelab, we were tasked with going through tutorial 4 which will have us design, layout and simuate a NAND gate.

To begin we create the NAND schematic.

   

Then we create the NAND symbol

 

 

Now we can simulate using our NAND symbol, we sim this circuit

 

 

And then we get these results

 

After that, we can layout the NAND gate. Below is layout, LVS check and DRC check

  

And extracted:

  

 

Labwork

Draft schematics, symbols, layouts and simulations of 2-NAND, 2-XOR, and Full Adder

 

NAND gate

We can reuse the 2-NAND gate from the prelab but with some modifications

 

NAND gate schematic and the corresponding symbol: 6u/0.6u

 

NAND Layout w/ DRC check and passing through LVS check.

   

And finally the extracted NAND

   

XOR gate

First we build the XOR schematic, and its corresponding symbol




Next we layout the XOR gate, and pass DRC and LVS check.


  

Extracted:

   

XOR/NAND Simulations

Using these gates, we can then observe the simulations for the inputs of: 00,01,10,11

Which gives us the following tables

 

ABAnandBAxorB
0010
0111
1011
1100
   

   

Full-adder

First we create the full-adder schematic and symbol

  

Next we create the full-adder layout, then DRC and LVS check.

Extracted full-adder:

Finally, we simulate our full-adder for all possible inputs

Which can then be converted to this table below.

ABCinSCout
00000
00110
01010
01101
10010
10101
11001
11111
We can notice that S and Cout have measurements where they are spiking to a different output. These can be ignored for this lab as they are due to the adder reading the fall/rise time of an input (A,B, or Cin).

  

  

 

Finally, as always, work getting backed up

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