EE 421L Fall 2021
Labs
| Lab1 | Cadence Introduction |
| Lab2 | Designing a 10-bit DAC |
| Lab3 | Layout of a 10-bit DAC |
| Lab4 | Layout of NMOS and PMOS Devices |
| Lab5 | Design, Layout, and Simulate a CMOS inverter |
| Lab6 | Design, Layout, and Simulate a CMOS NAND gate, XOR, gate, and Full-Adder |
| Lab7 | Using Buses and Arrays in the design of Word Inverters, Muxes, and High-speed Adders |
| Lab8 | Generating a Test Chip Layout for Fabrication |
| Project | Register File that contains 32 8-Bit Words |