Lab 2 - EE 421L
The purpose of Lab 2 is to utilize n-well resistors in order to create 10-bit Digital to Analog Converters.
The first step in this prelab was to unzip the lab2.zip file and upload it into the CMOSedu design directory.
After loading the file, I added DEFINE lab2 $HOME/CMOSedu/lab2 into my cds.lib file so that the I can access the lab2 files within the Cadence library manager.
In order to get a better understanding for what this circuit does, I launch the analog design environment. Inside the ADE, I ran the simulation which gave me the results seen below.
Determining the Least Significant Bit
The LSB is the minimum voltage change needed in order to alter the output of the ADC. To calculate this, we need to follow the equation seen below.
LSB = Vdd/(2^n)
Vdd is the source input that is running into into the ADC.
n is the number of bits that are being outputted by the ADC.
Since there are 10 bits being outputted from the ADC, 2^10 will give us the number of possible binary numbers.
By dividing Vdd by the total amount of possible binary numbers, we find our LSB.
Vdd = 5V
n = 10 bits
LSB = Vdd/(2^n)
LSB = 5/(2^10)
LSB = 4.8828mV
Based on my calculations, I found that the LSB is 4.8828mV. This means that incrementing the input of the ADC by 4.8828mV will cause the least significant bit of our ADC bus output (B[9:0]) to increase by 1.
To prove my calculations, I simulated a circuit in which Vin's amplitude was 10mV and the offset was 5mV. This gave the results seen below.
From the results seen above, it is easy to see that something is a little weird.
When the input to the ADC (Vin) goes above half of 4.88mV (around 2.44mV), we find that Vout (the output of the DAC) outputs 4.88mV.
Based upon this discovery, I can conclude that the ADC is created in such a way that allows the the ADC bus output (B[9:0]) to be determined based upon the nearest multiple of 4.88mV.
This means that when Vin = 7mV, Vout = 4.88mV since that is the closest multiple of 4.88mV.
However, when Vin = 7.5mV, Vout = 9.76mV since that now the closes multiple of 4.88mV
Understanding the ADC and DAC even further
To illustrate this point even further, I simulated circuits with a DC input of 2.4mV and 2.5mV so that we can see the change in Vout.
Below is the circuit with Vin = 2.4mV.
As we can see, Vout is 0V since the nearest multiple of 4.88mV is 0V.
Below is a circuit with Vin = 2.5mV.
As we can see, Vout is 4.88mVV since the nearest multiple of 4.88mV is 4.88mV when Vin = 2.5mV.
Lab
In this lab, I created a DAC by utilizing n-well resistors. The topology I used is shown below.
The first step is to create the voltage divider for a single bit.
After this, I made a symbol for the voltage divider so that I can more easily implement this voltage divider into my schematic.
I created the symbol by:
1. Clicking create
2. Clicking Cellview
3. Clicking from Cellview
4. Finally, a menu pops up. Click ok.
With these steps done, the inputs and outputs should be loaded onto a fresh page.
My final symbol is shown below.
With the symbol made for a single bit, I created the schematic for the 10-bit DAC. My schematic is shown below.
The final step was to create a symbol for the DAC.
The symbol for the DAC is displayed below.
Determining Output Resistance of DAC
Below are the steps I took in order to find the output resistance of the DAC.
First, I saw that 20k and 20k were in parallel which meant that the resulting resistance was 10k.
After noticing that the resistor was 10k, I realized that the 10k resistor above was in series meaning that a 20k resulted.
This means that I can iteratively solve this circuit until I got 10k ohms.
Determining Delay
I grounded all bits of the DAC besides B9 and connected a pulse source to B9 in order to find the delay. In addition, a 10pF capacitor was introduced as the load.
With B9 being high, this means that the output should be half of the input of B9. Since the input is 5V, the output max voltage should be 2.5V.
The delay will be found with the equation below.
delay = 0.7RC
delay = 0.7(10k)(10p)
delay = 70ns
Below is a simulation that proves that the delay should be 70ns.
Verifying the validity of the Design
In order to verify that the DAC is working correctly, the Ideal 10-bit DAC will be swapped for the DAC I created.
I ran simulations to prove that the design worked.
Since the simulations weren't working, I coerced the simulation to converge by:
1. Going to the Analog Design Environment
2. Clicking simulation
3. Hitting options
4. Clicking analog
5. Typing in the options shown below
Introducing a Load to the DAC
First, I used a load of 10k ohms. This caused the output voltage to be halved.
This makes sense since the output resistance of the DAC is 10k ohms.
The resulting voltage divider caused the output voltage to be 2.5V which is half of Vin.
Next, I implemented a 10p capacitor as the load. The capacitor smoothened the output, and introduced a delay to Vout.
Lastly, I introduced both a 10k resistor and a 10p capacitor to the load. This resulted in Vout's amplitude being reduced significantly due to the resistor, and Vout was delayed due to the capacitor.
MOSFET Discussion
If the circuit was real, the switches (outputs of the ADC) would be implemented with transistors (MOSFETs).
If the resistance of the switches are not small compared to the resistors (R) in the DAC, this means that the output voltage would be lower.
This is due to the fact that the switch would be in series with 2R augmenting its value.
The larger resistance means that the voltage drop would be larger causing Vout to be smaller.